forked from M-Labs/artiq
phaser: spelling
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@ -12,7 +12,7 @@ class DDSChannel(Module):
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enable_replace=True))
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to_rio_phy = ClockDomainsRenamer("rio_phy")
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self.submodules.dds = to_rio_phy(MultiDDS(
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n=5, fwidth=32, xwidth=16, z=19, zl=10, shae_lut=share_lut))
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n=5, fwidth=32, xwidth=16, z=19, zl=10, share_lut=share_lut))
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regs = []
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for i in self.dds.i:
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regs.extend([i.f, Cat(i.a, i.clr, i.p)])
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