forked from M-Labs/artiq
wrpll: fix mulshift (2)
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3f076bf79b
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d185f1ac67
@ -400,8 +400,11 @@ class NopUnit(BaseUnit):
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class OpUnit(BaseUnit):
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def __init__(self, op, data_width, stages):
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def __init__(self, op, data_width, stages, op_data_width=None):
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BaseUnit.__init__(self, data_width)
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# work around Migen's mishandling of Verilog's cretinous operator width rules
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if op_data_width is None:
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op_data_width = data_width
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if stages > 1:
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# Vivado backward retiming for DSP does not work correctly if DSP inputs
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@ -419,10 +422,11 @@ class OpUnit(BaseUnit):
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i0, i1, stb_i = self.i0, self.i1, self.stb_i
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output_stages = stages
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o = op(i0, i1)
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o = Signal((op_data_width, True))
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self.comb += o.eq(op(i0, i1))
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stb_o = stb_i
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for i in range(output_stages):
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n_o = Signal(data_width)
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n_o = Signal((data_width, True))
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if stages > 1:
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n_o.attr.add(("retiming_backward", 1))
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n_stb_o = Signal()
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@ -552,9 +556,8 @@ class ProcessorImpl(Module):
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if pd.multiplier_shifts:
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if len(pd.multiplier_shifts) != 1:
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raise NotImplementedError
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# work around Migen's mishandling of Verilog's cretinous operator width rules
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multiplier = OpUnit(lambda a, b: Cat(a, C(0, pd.data_width)) * Cat(b, C(0, pd.data_width)) >> pd.multiplier_shifts[0],
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pd.data_width, pd.multiplier_stages)
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multiplier = OpUnit(lambda a, b: a * b >> pd.multiplier_shifts[0],
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pd.data_width, pd.multiplier_stages, op_data_width=2*pd.data_width)
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else:
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multiplier = NopUnit(pd.data_width)
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minu = SelectUnit(operator.lt, pd.data_width)
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