forked from M-Labs/artiq
kasli2: work around vivado clock constraint problem
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96a5df0dc6
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7dfb4af682
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@ -587,14 +587,19 @@ class SatelliteBase(BaseSoC):
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self.submodules.wrpll_sampler = DDMTDSamplerGTP(
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self.drtio_transceiver,
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platform.request("cdr_clk_clean_fabric"))
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helper_clk_pads = platform.request("ddmtd_helper_clk")
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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helper_clk_pads=helper_clk_pads,
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
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# note: do not use self.wrpll.cd_helper.clk; otherwise, vivado craps out with:
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# critical warning: create_clock attempting to set clock on an unknown port/pin
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# command: "create_clock -period 7.920000 -waveform {0.000000 3.960000} -name
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# helper_clk [get_xlnx_outside_genome_inst_pin 20 0]
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platform.add_period_constraint(helper_clk_pads.p, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, helper_clk_pads.p)
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else:
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0"
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@ -616,7 +621,7 @@ class SatelliteBase(BaseSoC):
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gtp.txoutclk, gtp.rxoutclk)
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if with_wrpll:
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platform.add_false_path_constraints(
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self.wrpll.cd_helper.clk, gtp.rxoutclk)
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helper_clk_pads.p, gtp.rxoutclk)
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for gtp in self.drtio_transceiver.gtps[1:]:
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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