forked from M-Labs/artiq
metlino: increase number of DRTIO links
Seems OK with Vivado 2019.2.
This commit is contained in:
parent
d5c1eaa16e
commit
bd9eec15c0
|
@ -67,8 +67,7 @@ class Master(MiniSoC, AMPSoC):
|
|||
|
||||
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
|
||||
clock_pads=platform.request("cdr_clk_clean", 0),
|
||||
# use only a few channels to work around Vivado bug
|
||||
data_pads=[platform.request("mch_fabric_d", i) for i in range(3)],
|
||||
data_pads=[platform.request("mch_fabric_d", i) for i in range(11)],
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
self.csr_devices.append("drtio_transceiver")
|
||||
|
|
Loading…
Reference in New Issue