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wrpll.si549: initialize the clock divider to a sensible value

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hartytp 2020-10-07 10:11:25 +01:00 committed by Sebastien Bourdeauducq
parent e6ff2ddc32
commit d780faf4ac
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/wrpll/si549.py
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@ -255,7 +255,7 @@ class Si549(Module, AutoCSR):
self.gpio_out = CSRStorage(2)
self.gpio_oe = CSRStorage(2)
self.i2c_divider = CSRStorage(16, reset=2500)
self.i2c_divider = CSRStorage(16, reset=75)
self.i2c_address = CSRStorage(7)
self.errors = CSR(2)