srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

phaser: share_lut

Browse Source
This commit is contained in:
Robert Jördens 2020-09-07 16:06:35 +00:00
parent e69bb0aeb3
commit 8aaeaa604e
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/rtio/phy/phaser.py
View File

@ -6,13 +6,13 @@ from .fastlink import SerDes, SerInterface
class DDSChannel(Module):
def __init__(self, use_lut=None):
def __init__(self, share_lut=None):
self.rtlink = rtlink.Interface(
rtlink.OInterface(data_width=32, address_width=4,
enable_replace=True))
to_rio_phy = ClockDomainsRenamer("rio_phy")
self.submodules.dds = to_rio_phy(MultiDDS(
n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut))
n=5, fwidth=32, xwidth=16, z=19, zl=10, shae_lut=share_lut))
regs = []
for i in self.dds.i:
regs.extend([i.f, Cat(i.a, i.clr, i.p)])
@ -32,7 +32,7 @@ class Phaser(Module):
# share a CosSinGen LUT between the two channels
self.submodules.ch0 = DDSChannel()
self.submodules.ch1 = DDSChannel(use_lut=self.ch0.dds.mod.cs.lut)
self.submodules.ch1 = DDSChannel(share_lut=self.ch0.dds.mod.cs.lut)
n_channels = 2
n_samples = 8
n_bits = 14