forked from M-Labs/artiq
phaser: share_lut
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e69bb0aeb3
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8aaeaa604e
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@ -6,13 +6,13 @@ from .fastlink import SerDes, SerInterface
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class DDSChannel(Module):
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def __init__(self, use_lut=None):
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def __init__(self, share_lut=None):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=4,
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enable_replace=True))
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to_rio_phy = ClockDomainsRenamer("rio_phy")
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self.submodules.dds = to_rio_phy(MultiDDS(
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n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut))
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n=5, fwidth=32, xwidth=16, z=19, zl=10, shae_lut=share_lut))
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regs = []
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for i in self.dds.i:
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regs.extend([i.f, Cat(i.a, i.clr, i.p)])
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@ -32,7 +32,7 @@ class Phaser(Module):
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# share a CosSinGen LUT between the two channels
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self.submodules.ch0 = DDSChannel()
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self.submodules.ch1 = DDSChannel(use_lut=self.ch0.dds.mod.cs.lut)
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self.submodules.ch1 = DDSChannel(share_lut=self.ch0.dds.mod.cs.lut)
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n_channels = 2
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n_samples = 8
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n_bits = 14
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