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wrpll: fix scl signal

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cw-mlabs 2020-07-27 12:57:29 +08:00 committed by Sébastien Bourdeauducq
parent 9b44ec7bc6
commit 8dd9a6d024
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/drtio/wrpll/si549.py
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@ -296,8 +296,8 @@ class Si549(Module, AutoCSR):
ts_scl.o.eq(self.gpio_out.storage[0]),
ts_scl.oe.eq(self.gpio_oe.storage[0])
).Else(
ts_scl.o.eq(programmer.scl),
ts_scl.oe.eq(1)
ts_scl.o.eq(0),
ts_scl.oe.eq(~programmer.scl)
)
]