forked from M-Labs/artiq
wrpll: fix scl signal
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9b44ec7bc6
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8dd9a6d024
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@ -296,8 +296,8 @@ class Si549(Module, AutoCSR):
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ts_scl.o.eq(self.gpio_out.storage[0]),
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ts_scl.oe.eq(self.gpio_oe.storage[0])
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).Else(
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ts_scl.o.eq(programmer.scl),
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ts_scl.oe.eq(1)
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ts_scl.o.eq(0),
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ts_scl.oe.eq(~programmer.scl)
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)
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]
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