forked from M-Labs/artiq
phaser: wire up multidds
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d1be1212ab
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e5e2392240
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@ -48,7 +48,7 @@ class Phaser:
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def __init__(self, dmgr, channel_base, miso_delay=1,
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core_device="core"):
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self.channel_base = channel_base << 8
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self.channel_base = channel_base
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self.core = dmgr.get(core_device)
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self.miso_delay = miso_delay
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# frame duration in mu (10 words, 8 clock cycles each 4 ns)
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@ -69,7 +69,7 @@ class Phaser:
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:param addr: Address to write to.
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:param data: Data to write.
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"""
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rtio_output(self.channel_base | addr | 0x80, data)
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rtio_output((self.channel_base << 8) | addr | 0x80, data)
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delay_mu(int64(self.t_frame))
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@kernel
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@ -81,8 +81,8 @@ class Phaser:
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:param addr: Address to read from.
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:return: The data read.
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"""
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rtio_output(self.channel_base | addr, 0)
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response = rtio_input_data(self.channel_base >> 8)
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rtio_output((self.channel_base << 8) | addr, 0)
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response = rtio_input_data(self.channel_base)
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return response >> self.miso_delay
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@kernel
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@ -199,3 +199,14 @@ class Phaser:
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self.spi_write(data)
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delay_mu(t_xfer)
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return data
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@kernel
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def set_frequency_mu(self, ch, osc, ftw):
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1)
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rtio_output(addr, ftw)
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@kernel
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def set_amplitude_phase_mu(self, ch, osc, asf=0x7fff, pow=0, clr=0):
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1) | 1
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data = (asf & 0x7fff) | (clr << 15) | (pow << 16)
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rtio_output(addr, data)
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@ -646,11 +646,12 @@ class Phaser(_EEM):
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def add_std(cls, target, eem, iostandard="LVDS_25"):
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cls.add_extension(target, eem, iostandard=iostandard)
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phy = phaser.Phaser(target.platform.request("phaser{}_ser_p".format(eem)),
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phy = phaser.Phaser(
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target.platform.request("phaser{}_ser_p".format(eem)),
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target.platform.request("phaser{}_ser_n".format(eem)))
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target.submodules += phy
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target.rtio_channels.extend([
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rtio.Channel.from_phy(phy, ififo_depth=4),
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rtio.Channel.from_phy(phy.dds0),
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rtio.Channel.from_phy(phy.dds1),
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rtio.Channel.from_phy(phy.ch0),
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rtio.Channel.from_phy(phy.ch1),
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])
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@ -6,22 +6,48 @@ from .fastlink import SerDes, SerInterface
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class DDSChannel(Module):
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def __init__(self):
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def __init__(self, use_lut=None):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=4,
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enable_replace=True))
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self.submodules.dds = MultiDDS(n=5, fwidth=32, xwidth=16)
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enable_replace=True))
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to_rio_phy = ClockDomainsRenamer("rio_phy")
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self.submodules.dds = to_rio_phy(MultiDDS(
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n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut))
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# TODO: latency
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self.comb += self.dds.stb.eq(1)
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regs = []
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for i in self.dds.i:
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regs.extend([i.f, Cat(i.a, i.clr, i.p)])
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data)
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)
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]
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class Phaser(Module):
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def __init__(self, pins, pins_n):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=8, address_width=8,
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enable_replace=False),
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enable_replace=False),
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rtlink.IInterface(data_width=10))
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self.submodules.dds0 = DDSChannel()
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self.submodules.dds1 = DDSChannel()
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self.submodules.ch0 = DDSChannel()
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self.submodules.ch1 = DDSChannel(use_lut=self.ch0.dds.mod.cs.lut)
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n_channels = 2
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n_samples = 8
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n_bits = 14
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body = [Signal(n_channels*2*n_bits, reset_less=True)
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for i in range(n_samples)]
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i_sample = Signal(max=n_samples)
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self.sync.rio_phy += [
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If(self.ch0.dds.valid, # & self.ch1.dds.valid,
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Array(body)[i_sample].eq(Cat(
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self.ch0.dds.o.q[2:], self.ch0.dds.o.i[2:],
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self.ch1.dds.o.q[2:], self.ch1.dds.o.i[2:])),
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i_sample.eq(i_sample + 1),
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),
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]
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self.submodules.serializer = SerDes(
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n_data=8, t_clk=8, d_clk=0b00001111,
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@ -31,6 +57,11 @@ class Phaser(Module):
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Cat(self.intf.data[:-1]).eq(Cat(self.serializer.data[:-1])),
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self.serializer.data[-1].eq(self.intf.data[-1]),
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]
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self.sync.rio_phy += [
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If(self.serializer.stb,
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i_sample.eq(0),
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),
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]
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header = Record([
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("we", 1),
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@ -38,10 +69,6 @@ class Phaser(Module):
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("data", 8),
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("type", 4)
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])
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n_channels = 2
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n_samples = 8
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n_bits = 14
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body = [Signal(n_bits) for i in range(n_channels*n_samples*2)]
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assert len(Cat(header.raw_bits(), body)) == \
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len(self.serializer.payload)
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self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
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