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792 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq a155a481b1 rtio/sed: add top-level core 2017-09-16 14:04:56 +08:00
Sebastien Bourdeauducq 92c63ce2e4 rtio/sed: rename fifos/gates, refactor tsc 2017-09-16 14:03:48 +08:00
Sebastien Bourdeauducq ac52c7c818 rtio/sed/LaneDistributor: style 2017-09-16 14:02:37 +08:00
Sebastien Bourdeauducq 7b299ba583 rtio/sed: remove obsolete ofifo_depth from test_output_driver 2017-09-16 14:01:19 +08:00
Sebastien Bourdeauducq 6b7a1893c7 rtio/sed/OutputDriver: support channels with different fine timestamp widths 2017-09-16 10:53:30 +08:00
Sebastien Bourdeauducq f39ee7ad62 rtio/sed: fix seqn_width 2017-09-16 10:52:37 +08:00
Sebastien Bourdeauducq 064503f224 rtio/sed/LaneDistributor: support specifying existing CRI 2017-09-16 10:52:13 +08:00
Sebastien Bourdeauducq 1cb05f3ed5 rtio/sed/LaneDistributor: persist underflow/sequence error until next write 2017-09-16 10:51:44 +08:00
Sebastien Bourdeauducq 3c922463a0 style 2017-09-15 15:36:46 +08:00
Sebastien Bourdeauducq 8e5ab90129 rtio/sed: add FIFO wrapper 2017-09-15 15:36:34 +08:00
Sebastien Bourdeauducq 490c9815a2 rtio/sed: add TSC/gate (untested) 2017-09-14 19:53:21 +08:00
Sebastien Bourdeauducq 181cb42ba8 rtio/sed: centralize all layouts in one file 2017-09-14 19:52:31 +08:00
Sebastien Bourdeauducq 1b61442bc3 rtio/sed: fix lane spreading and enable by default 2017-09-13 22:48:10 +08:00
Sebastien Bourdeauducq 8cfe2ec53a rtio/sed: fix sequence number width computation 2017-09-13 22:11:41 +08:00
Sebastien Bourdeauducq a92a955d1e rtio/sed: use __all__ 2017-09-13 18:17:22 +08:00
Sebastien Bourdeauducq feec6298a5 rtio/sed: add lane distributor simulation unittest 2017-09-13 18:00:16 +08:00
Sebastien Bourdeauducq c74abccfd5 rtio/sed: lane distributor fixes 2017-09-13 17:50:06 +08:00
Sebastien Bourdeauducq bdd96084c5 rtio/sed: add lane distributor (untested) 2017-09-13 00:07:26 +08:00
Sebastien Bourdeauducq faf54127ac rtio/sed: remove VCD fine in unittest 2017-09-11 23:07:09 +08:00
Sebastien Bourdeauducq a2b7894134 rtio/sed: add output driver simulation unittest 2017-09-11 23:05:10 +08:00
Sebastien Bourdeauducq 00ff3f5b0d rtio/sed: fix output driver busy output 2017-09-11 23:04:52 +08:00
Sebastien Bourdeauducq 64d9381c36 rtio/sed: remove uneeded yield in test_sed_output_network 2017-09-11 23:02:56 +08:00
Sebastien Bourdeauducq 666bc600a2 rtio/sed: add output driver (untested) 2017-09-11 11:10:28 +08:00
Sebastien Bourdeauducq 1d2ebbe60f rtio/sed: make ON payload layout configurable, add latency function 2017-09-11 09:06:40 +08:00
Sebastien Bourdeauducq 527b403bb1 rtio/sed: add output network simulation unittest 2017-09-10 23:41:20 +08:00
Sebastien Bourdeauducq c5d6a2ba1a rtio/sed: more output network fixes 2017-09-10 23:41:04 +08:00
Sebastien Bourdeauducq 96505a1cd9 rtio/sed: output network fixes 2017-09-10 23:23:10 +08:00
Sebastien Bourdeauducq 5646e19dc3 rtio/sed: add output network (untested) 2017-09-10 14:38:43 +08:00
Florent Kermarrec 2091c7696a artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode 2017-09-06 09:18:12 +02:00
Sebastien Bourdeauducq 9edff2c520 remote_csr: interpret length as CSR size, not number of bus words 2017-08-31 13:34:48 +08:00
Sebastien Bourdeauducq 0a5904bbaa firmware: support for multiple JESD DACs 2017-08-31 13:05:48 +08:00
Sebastien Bourdeauducq a4144a07c4 sayma_amc: add converter SPI config defines 2017-08-31 13:04:38 +08:00
Sebastien Bourdeauducq bacf8a1614 style 2017-08-31 12:52:09 +08:00
Sebastien Bourdeauducq ad0a940e2d sayma_rtm: hook up DAC SPI 2017-08-31 11:48:54 +08:00
Sebastien Bourdeauducq f765dc50de sayma_rtm: do not keep DACs in reset 2017-08-31 11:44:33 +08:00
Sebastien Bourdeauducq a67659338d sayma: clean up serwb comments 2017-08-31 11:42:01 +08:00
Florent Kermarrec 660f9856ec gateware/serwb: add test for phy initialization 2017-08-30 17:59:10 +02:00
Florent Kermarrec 9650233007 gateware/serwb: change serdes clock domain to serwb_serdes 2017-08-30 15:44:44 +02:00
Florent Kermarrec 32ca51faee gateware/targets/sayma_amc_standalone/rtm: use new serwb modules 2017-08-30 15:25:20 +02:00
Florent Kermarrec 41d57d64f6 gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
Florent Kermarrec 9ba50098a8 gateware/test/serwb: use unittest for in test_etherbone 2017-08-29 17:31:01 +02:00
Florent Kermarrec 7d7f6be7ce gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction 2017-08-29 16:41:29 +02:00
Florent Kermarrec 60ad36e7d6 gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready 2017-08-29 13:43:26 +02:00
Florent Kermarrec 89558e2653 gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors 
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
 2017-08-29 13:38:52 +02:00
Sebastien Bourdeauducq 26a11a296c sayma_rtm: drive DAC control signals 2017-08-26 16:57:02 -07:00
Sebastien Bourdeauducq d609c67cbd sayma_rtm: set clock mux pins 2017-08-26 16:48:10 -07:00
Sebastien Bourdeauducq 9194402ea5 sayma_rtm: expose HMC SPI bus 2017-08-26 16:31:31 -07:00
Sebastien Bourdeauducq dbc12540da sayma_amc: register RTM CSR regions from CSV 2017-08-26 14:48:11 -07:00
Sebastien Bourdeauducq 54c75d3274 sayma_rtm: use CSR infrastructure, generate CSR CSV 2017-08-23 17:19:53 -04:00
Sebastien Bourdeauducq 668450db26 sayma_amc: add serwb 2017-08-21 18:11:29 -04:00
Sebastien Bourdeauducq 0459a70cf6 sayma_amc: cleanup, fix RTM UART forwarding 2017-08-21 16:49:42 -04:00
Sebastien Bourdeauducq 1f2b373d09 sayma_rtm: remove unnecessary serwb_control 2017-08-21 16:37:13 -04:00
Sebastien Bourdeauducq bfea297279 targets: add Sayma RTM 2017-08-21 15:58:01 -04:00
Sebastien Bourdeauducq 53c7f92fdc serwb: add __init__.py and expose submodules 2017-08-21 15:57:43 -04:00
Sebastien Bourdeauducq dac3a78b75 serwb: style, use migen, fix imports 2017-08-21 12:35:59 -04:00
Florent Kermarrec da90a0fa12 Add test for Etherbone 
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
 2017-08-21 12:31:49 -04:00
Florent Kermarrec 44dc76e42e Add serial Wishbone bridge 
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
 2017-08-21 12:22:05 -04:00
Sebastien Bourdeauducq d6b624dfbe sayma_amc: connect RTM serial and second serial 2017-08-20 19:01:55 -04:00
Sebastien Bourdeauducq bee4902323 add Sayma AMC standalone target 2017-08-20 11:47:45 -04:00
Sebastien Bourdeauducq 1dab7df846 kc705_sma_spi: fix permissions 2017-08-20 10:54:24 -04:00
Sebastien Bourdeauducq df4f38a1e4 kc705: add pullup on SD card MISO 2017-07-24 22:26:16 +08:00
Sebastien Bourdeauducq a201a9abd9 drtio: multilink transceiver interface 2017-07-18 13:27:33 +08:00
Sebastien Bourdeauducq 9045b4cc19 drtio: initial firmware support for multi-link 2017-07-18 00:40:21 +08:00
Sebastien Bourdeauducq 4deb5f6a45 gateware: use new MiSoC Wishbone address system 2017-07-13 19:16:49 +08:00
mntng 40ca951750 kc705: add SPI bus for memory card 
This will be useful for SPI unit tests using a SD card as victim.
 2017-07-12 00:27:44 +08:00
Robert Jördens 7b130a2c32 sawg: confirm smooth(order=3) 2017-07-07 11:36:03 +02:00
Robert Jördens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" 
This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
 2017-07-04 17:55:19 +02:00
Robert Jördens 8e0a1cbdc8 sawg: advance dds 1/2 by one sample group 
closes #772
 2017-07-04 16:51:58 +02:00
Robert Jördens 91ca9fbcad sawg: also give offset some headroom 
closes #771
 2017-07-04 16:50:06 +02:00
Robert Jördens 78d1f0fdf6 sawg: fix PhasedAccu resets 2017-07-04 11:56:21 +02:00
Florent Kermarrec 2910b1be5e artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect 2017-07-04 10:48:06 +02:00
Sebastien Bourdeauducq 838127d914 rtio: break DMA timing path 2017-07-02 10:24:01 +08:00
Robert Jördens 911ee4a959 rtio: make pipelined logic reset_less 
* latency-corrected counters
* registered error logic
 2017-06-29 12:55:32 +02:00
Robert Jördens 600a48ac61 dsp.fir: cleanup 2017-06-29 12:18:48 +02:00
Robert Jördens dca662a743 dsp.fir: pipeline final systolic adder 2017-06-29 11:33:19 +02:00
Robert Jördens 32a33500c8 dsp.fir: actively cull zero delays 2017-06-29 11:24:56 +02:00
Robert Jördens f520d4a768 rtio: undo _RelaxedAsyncResetSynchronizer 2017-06-28 22:08:15 +02:00
Robert Jördens 3cbbcdfe96 sawg: don't enable_replace for Config 
closes #762
 2017-06-28 20:31:40 +02:00
Robert Jördens f2632e0fd1 sawg: adapt latency to fir changes 
closes #748
 2017-06-28 20:12:30 +02:00
Robert Jördens e7db2c6578 dsp.accu: reset_less outputs 2017-06-28 20:04:58 +02:00
Robert Jördens 6bb994228f dsp.fir: drop x shift 2017-06-28 19:55:15 +02:00
Robert Jördens 01847271c5 rtio: use reset_less signal for reset fanout 2017-06-28 19:43:55 +02:00
Robert Jördens b9859cc0c3 dsp.fir: remove old/wrong comment 2017-06-28 19:21:57 +02:00
Robert Jördens 55b5b87490 fir: simplify latency compensation 
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
 2017-06-28 19:13:43 +02:00
Robert Jördens d1e5dd334f sawg: use pipeline reset 2017-06-28 19:09:39 +02:00
Robert Jördens 6418205906 dsp.fir: use pipelin-reset 2017-06-28 19:09:21 +02:00
Robert Jördens 07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
Robert Jördens f78d5a87e9 dsp/test: skip and fix sat_add 2017-06-22 18:01:31 +02:00
Robert Jördens 47928a2c0d sawg: disable limiter 
temporary workaround to permit testing other aspects
 2017-06-22 17:31:04 +02:00
Robert Jördens cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
Robert Jördens 9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
Robert Jördens d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
Robert Jördens 694f8d784c dsp/tools: unittest sat_add 2017-06-22 11:29:56 +02:00
Robert Jördens bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
Robert Jördens cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
Robert Jördens 5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
Robert Jördens 570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
Robert Jördens 4b3aad2563 sawg: clean up Config 
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
 2017-06-22 10:26:29 +02:00
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Robert Jördens ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
Robert Jördens b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
Sebastien Bourdeauducq 74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
Robert Jördens 0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
Robert Jördens 424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
Robert Jördens 219dfd8984 rtio: add one register level for rio and rio_phy resets 
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
 2017-06-17 12:17:48 +02:00
Robert Jördens e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
Robert Jördens 2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
Robert Jördens 3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
Robert Jördens e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
Robert Jördens 315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
Robert Jördens 9a8a7b9102 sawg: handle clipping interpolator 
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
 2017-06-12 20:33:54 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens bfc224d4ba phaser: adjust to new jesd 2017-05-22 19:59:53 +02:00
Robert Jördens 679060af1d phaser: enable dma 2017-05-22 19:32:34 +02:00
Robert Jördens 4901cb9a8a sawg: fix clr width 2017-05-22 17:46:55 +02:00
Robert Jördens 253ee950f6 sawg: fix config channel addr 2017-05-22 17:45:14 +02:00
Sebastien Bourdeauducq 9ab63920e0 Remove Pipistrello support 
Closes #658
Closes #381
 2017-05-15 17:17:44 +08:00
Robert Jördens 170d2886fd Merge branch 'pdq' 
* pdq:
  pdq: documentation
  pdq2 -> pdq
  pdq2: use 16 bit data, buffered read_mem()
  spi: style
  pdq2: mem_read
  pdq2: align subsequent writes to end
  sma_spi: undo cri_con
  pdq2: memory write, kernel_invariants
  sma_spi: cri/cd changes
  sma_spi: LVCMOS25
  coredevice.spi: kernel invariants and style
  sma_spi: free up user_sma pins
  sma_spi: add demo target with SPI on four SMA
  pdq2: memory write
  pdq2: crc/frame register accessors
  doc: pdq2 spi backend
  pdq2: config writes
 2017-05-12 11:46:45 +02:00
Florent Kermarrec 79c339d4ac gateware/targets/phaser: jesd core now handles jsync completely 2017-04-26 22:25:08 +02:00
Florent Kermarrec 0546affd4c gateware/target/phaser: jesd start signal renamed to jsync 2017-04-26 12:27:40 +02:00
Robert Jördens ed8edf318d sma_spi: undo cri_con 2017-04-08 17:19:35 +02:00
Robert Jördens 16b7f8f50c sma_spi: cri/cd changes 2017-04-08 17:16:19 +02:00
Robert Jördens 1e6e81a19e sma_spi: LVCMOS25 2017-04-08 17:16:19 +02:00
Robert Jördens 555b3c38c1 sma_spi: free up user_sma pins 2017-04-08 17:16:19 +02:00
Robert Jördens 2c7c6143ab sma_spi: add demo target with SPI on four SMA 2017-04-08 17:16:19 +02:00
Sebastien Bourdeauducq c2667debf8 drtio: test replace in RTL simulation 2017-04-06 16:33:59 +08:00
Sebastien Bourdeauducq 729e7b52f0 drtio: collision/replace fixes 2017-04-06 16:33:49 +08:00
Sebastien Bourdeauducq 83d87b5805 drtio: remove outdated comment 2017-04-06 12:45:10 +08:00
Sebastien Bourdeauducq c0100ebc56 rtio: fix indentation 2017-04-06 12:08:13 +08:00
Sebastien Bourdeauducq 207453efcd rtio: add a missing case for collision reporting 2017-04-06 11:28:16 +08:00
Sebastien Bourdeauducq 674bf82f3a gateware: add cri_con CSRs to all DMA-capable targets 2017-04-06 01:14:09 +08:00
Sebastien Bourdeauducq 5e3aef45dc drtio: support collision/replace + detect sequence errors at satellite 2017-04-06 01:06:56 +08:00
whitequark 17b5388259 gateware: remove one stray CRI arbiter remnant. 2017-04-05 16:38:56 +00:00
whitequark 464202d0aa gateware: connect CRI switch to kernel CPU. 2017-04-05 16:10:53 +00:00
whitequark 47632f81b1 gateware: CRIArbiter -> CRISwitch. 2017-04-05 16:10:39 +00:00
whitequark 391660e545 gateware: simplify the CRI arbiter to use a plain mux. 2017-04-05 15:09:19 +00:00
Sebastien Bourdeauducq 12249dac57 rtio: do not clear asynchronous error flags on RTIO reset 2017-04-03 00:20:30 +08:00
Sebastien Bourdeauducq db3118b916 drtio: use BlindTransfer for error reporting 2017-04-03 00:18:07 +08:00
Sebastien Bourdeauducq 8c414cebc7 drtio: report busy errors 2017-04-03 00:11:08 +08:00
Sebastien Bourdeauducq 008678b741 drtio: add infrastructure for reporting busy/collision errors 2017-04-02 23:45:55 +08:00
Sebastien Bourdeauducq 0a687b7902 drtio: report satellite errors through firmware 2017-04-01 12:18:00 +08:00
Sebastien Bourdeauducq 28211e0b32 gateware: reset RTIO DMA core when kernel CPU is reset 2017-03-31 15:35:28 +08:00
Sebastien Bourdeauducq 200c499114 test: change base address in DMA simulation testbench 2017-03-31 13:17:00 +08:00
Sebastien Bourdeauducq ea3af1e20e drtio: remove obsolete CSR accesses from test 2017-03-27 16:44:22 +08:00
Sebastien Bourdeauducq b74d6fb9ba make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
whitequark 4de336fbe9 gateware: reverse bytes of SDRAM word, not bits. 2017-03-17 11:16:46 +00:00
whitequark 6b63322106 gateware: reverse SDRAM words in RTIO DMA engine. 2017-03-17 07:29:28 +00:00
whitequark 4b14887ddb gateware: work around ISE/Vivado bugs with very wide shifts. 2017-03-17 07:29:28 +00:00
whitequark 4beda73217 firmware: don't build libdyld through misoc. 2017-03-14 08:33:31 +00:00
Sebastien Bourdeauducq a7de58b604 rtio: Inout → InOut 2017-03-14 14:18:55 +08:00
Sebastien Bourdeauducq 13ae1d1a38 drtio: input unittest 2017-03-14 14:14:55 +08:00
Sebastien Bourdeauducq 56fd9b3b4b drtio: input fixes 2017-03-14 14:14:43 +08:00
Sebastien Bourdeauducq 95ede18809 drtio: support PHY latency compensation 2017-03-14 00:01:38 +08:00
Sebastien Bourdeauducq 497c795d8c drtio: input support (untested) 2017-03-13 23:54:44 +08:00
Sebastien Bourdeauducq d1b9f9d737 drtio: rt_packets → rt_packet 2017-03-13 00:10:07 +08:00
Sebastien Bourdeauducq 6b7c781ff2 drtio: introduce 'standard request' interface in RT packet layer 2017-03-13 00:08:03 +08:00
Sebastien Bourdeauducq 2b8729f326 drtio: clear any read request on satellite reset 2017-03-13 00:00:38 +08:00
Sebastien Bourdeauducq 1e47e638bb drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
Sebastien Bourdeauducq 1e6a33b586 rtio: handle input timeout in gateware 
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
 2017-03-03 17:37:47 +08:00
Sebastien Bourdeauducq d2f2415b50 analyzer: use CRI and connect at RTIO core 
This causes DMA events to be included in analyzer traces.
 2017-03-02 18:47:56 +08:00
Sebastien Bourdeauducq 7d6ebabc1b reorganize core device communication code 2017-02-27 18:37:30 +08:00
Sebastien Bourdeauducq f017d1771f gateware: remove unused configs in targets (not needed with new moninj) 2017-02-25 12:14:56 +08:00
Sebastien Bourdeauducq 360be0098f drtio: map local RTIO core on lower channels 2017-02-24 18:15:27 +08:00
Sebastien Bourdeauducq b455ea447d gateware: add moninj to drtio targets 2017-02-21 21:54:47 +08:00
Sebastien Bourdeauducq c66efc0279 moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
Robert Jördens c022b53578 kernel_cpu: enable perf counters 2017-02-18 14:09:12 +01:00
Sebastien Bourdeauducq 935799dfb7 drtio: fix satellite transceiver clocking 2017-02-04 19:18:35 +08:00
whitequark b9cbedceb1 firmware: migrate last vestiges of the old runtime build system. 2017-02-03 12:59:35 +00:00
Sebastien Bourdeauducq a8ecbd6041 firmware: do not attempt to build Si5324 code when gateware does not support it 2017-02-03 12:27:13 +08:00
Sebastien Bourdeauducq d181989de9 drtio: reset Si5324 at each boot 2017-02-03 12:00:58 +08:00
Sebastien Bourdeauducq b3697f951a drtio: forward clocks to SMA connectors for debugging 2017-02-03 12:00:36 +08:00
Sebastien Bourdeauducq aafefee7f5 targets: make number of ethmac slots consistent 2017-02-02 23:02:51 +08:00
whitequark 44a9a79f96 firmware: port allocator to Rust. 2017-02-02 10:55:35 +00:00
Sebastien Bourdeauducq f512ea42dc drtio: initialize si5324 in firmware 2017-02-02 18:11:24 +08:00
whitequark b95db4fa4e Use four ethmac buffers instead of two. 
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
 2017-01-30 07:42:27 +00:00
Sebastien Bourdeauducq 9800acea92 drtio: program Si5324 for 150MHz in 3G config 2017-01-30 14:50:12 +08:00
Sebastien Bourdeauducq 7daab07a29 drtio: fix syntax/import 2017-01-30 13:01:45 +08:00
Sebastien Bourdeauducq d8e9949266 drtio: initialize AD9516 clock chip 2017-01-30 11:06:45 +08:00
Sebastien Bourdeauducq f6024b6c9a drtio: fix ad9154 extension registration 2017-01-30 10:59:22 +08:00
Sebastien Bourdeauducq 43aad0914e python3.5 -> python3 
Many things also work with Python 3.6.
 2017-01-30 09:24:43 +08:00
Sebastien Bourdeauducq 657afd770e artiq/test/gateware -> artiq/gateware/test 
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
 2017-01-30 09:00:55 +08:00
Sebastien Bourdeauducq 94b0783897 drtio: remove support for transceiver SMAs 
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
 2017-01-27 23:33:50 +08:00
whitequark de17908b38 Revert "Globally update UART baudrate to 921600." 
This reverts commit b29e2d5bfe.

This broke flterm firmware upload, which was the entire point
of the whole exercise.
 2017-01-25 00:31:28 +00:00
whitequark b29e2d5bfe Globally update UART baudrate to 921600. 2017-01-24 22:25:58 +00:00
whitequark 527b1e986c firmware: integrate smoltcp instead of lwip. 2017-01-23 13:59:34 +00:00
Sebastien Bourdeauducq 28a41a2f60 gateware: fix aeb1ba847 2017-01-18 17:11:02 -06:00
Sebastien Bourdeauducq 2a7a8f91ca gateware: fix import 2017-01-18 16:51:30 -06:00
Sebastien Bourdeauducq ce31ffddb0 firmware: add satellite manager 
The code duplication with the runtime should be cleaned up later.
 2017-01-18 16:50:32 -06:00
Sebastien Bourdeauducq b40953800a gateware: soc -> amp.soc 2017-01-18 15:28:14 -06:00
Sebastien Bourdeauducq aeb1ba8471 gateware: use default MiSoC timer 2017-01-18 15:22:33 -06:00
Sebastien Bourdeauducq b8d89d56b1 drtio: add GenericRXSynchronizer 2017-01-15 13:44:43 -06:00
Sebastien Bourdeauducq 0edffb54c2 drtio: fix packet truncation detection in RTPacketSatellite 2017-01-13 09:29:22 -06:00
Sebastien Bourdeauducq 6805feb494 drtio: report truncated packets 2017-01-12 23:44:45 -06:00
Sebastien Bourdeauducq 7c699e2f80 drtio: add FIFO space request count debug API 2017-01-11 13:48:14 -06:00
Sebastien Bourdeauducq c25186fae1 drtio: print packet error descriptions in log 2017-01-10 18:03:01 -06:00
Sebastien Bourdeauducq 98598df78e rtio: keep retrying on get FIFO space timeout 2017-01-10 16:12:32 -06:00
Sebastien Bourdeauducq e624f45369 drtio: remove FIFO empty local detection optimization 
It optimizes a marginal case, it is difficult to get right
(need to know the size of the FIFO for each channel), and
it adds complexity and potential bug sources.
 2017-01-10 14:31:46 -06:00