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969 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 53facfef13 sayma: build fixes 2018-01-22 18:33:22 +08:00
Sebastien Bourdeauducq 25f3feeda8 refactor targets 2018-01-22 18:25:10 +08:00
Sebastien Bourdeauducq 5198c224a2 sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
Florent Kermarrec 8fe463d4a0 sayma_rtm: add UART loopback to easily know if rtm fpga is alive 2018-01-20 06:04:34 +01:00
Florent Kermarrec 74ce7319d3 sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?) 2018-01-20 06:04:18 +01:00
Florent Kermarrec d27727968c add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
Sebastien Bourdeauducq cdbf95d46a kasli: fix permissions 2018-01-19 18:31:20 +08:00
Robert Jördens 8ec33ae7bd kasli: feed EEM clock fan-out from SI5324 2018-01-17 17:27:59 +01:00
Robert Jördens ed3e3b2791 sayma_amc: clarify --with-sawg help 2018-01-17 12:10:30 +01:00
Florent Kermarrec f54b27b79c sayma_amc: prepare for jesd subclass 1 2018-01-17 11:49:36 +01:00
Florent Kermarrec f73c3e5944 gateware/test/serwb: update and cleanup test (v2...) 2018-01-16 20:06:43 +01:00
Robert Jördens 7405006668 sayma: rtio clock is jesd fabric clock 2018-01-16 18:19:04 +01:00
whitequark 247167d34a Revert "gateware/test/serwb: update and cleanup tests" 
This reverts commit 5b03cc2fae.
 2018-01-16 08:21:26 +00:00
whitequark 444b901dbe sayma: add RTM configuration port. 2018-01-16 07:28:00 +00:00
Florent Kermarrec 5b03cc2fae gateware/test/serwb: update and cleanup tests 2018-01-15 21:53:40 +01:00
whitequark 6891141fa6 artiq_flash: add sayma support. 2018-01-15 11:43:29 +00:00
Robert Jördens 529033e016 kernel_cpu: disable PCU 
* contributes to long timing paths on artix 7 (kasli)
* currently only used for testing and debugging
 2018-01-12 12:03:50 +00:00
Robert Jördens ac3c3871d0 kasli: s/extensions/variant/g 2018-01-12 12:29:42 +01:00
Sebastien Bourdeauducq 7c82fcf41a targets: avoid passing cpu_type around unnecessarily 2018-01-11 11:21:55 +08:00
Sebastien Bourdeauducq 6d58c4390b Merge branch 'sed-merge' 2018-01-10 13:14:39 +08:00
Sebastien Bourdeauducq 04b2fd3e13 sayma: fix AD9154NoSAWG ramp clock domain 2018-01-10 12:11:33 +08:00
Sebastien Bourdeauducq dc593ec0f0 Merge branch 'rtio-sed' into sed-merge 2018-01-10 12:04:54 +08:00
Florent Kermarrec 2009734b3c serwb/phy: get 625Mbps linerate working, increase timeout 2018-01-09 18:54:52 +01:00
Florent Kermarrec 9c6a7f7509 serwb/kusphy: use same serwb_serdes_5x reset than s7phy 2018-01-09 18:54:05 +01:00
Robert Jördens 8813aee6b1 targets: add kasli [wip, untested] 2018-01-04 16:12:12 +01:00
Florent Kermarrec 1e972034e8 gateware/targets: enable serwb scrambling on sayma amc & rtm 2018-01-03 17:34:46 +01:00
Florent Kermarrec 907af25a69 gateware/serwb: add scrambling, reduce cdc fifo depth 2018-01-03 17:34:03 +01:00
Florent Kermarrec 7f4756a869 gateware/serwb: cleanup packet 2018-01-03 17:30:12 +01:00
Robert Jördens c2be820e9a kc705_dds: make ext_clkout 100 MHz 2018-01-02 19:58:47 +01:00
Robert Jördens 43686f324b kc705_dds: fix HPC voltages 
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V

* the direction control register on HPC (FMC-DIO to VHDCI)
  was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
  they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
  and hope for the best.
 2018-01-02 13:41:07 +01:00
Robert Jördens 94b84ebe7c kc705_dds: add urukul spi/ttl channels 2018-01-02 13:20:48 +01:00
Robert Jördens 53969d3686 kc705_dds: add urukul on vhdci extension definition 2018-01-02 13:20:47 +01:00
Robert Jördens 2f8e6c7462 spi: add diff_term, save power on outputs 2018-01-02 13:20:47 +01:00
Robert Jördens 6d20b71dde ttl_serdes_7series: refactor IOSERDES 2018-01-02 13:20:47 +01:00
Robert Jördens 745e695b09 sayma: output a ramp in the absence of SAWG channels 2017-12-31 12:18:53 +01:00
whitequark a371b25525 bootloader: allow using without Ethernet. 2017-12-31 09:21:28 +00:00
Sebastien Bourdeauducq 6e0288e568 drtio: fix GTH CPLL reset 2017-12-30 12:14:36 +08:00
Robert Jördens 379d29561b sayma: plausibility assertion on sawg data stream 2017-12-29 19:15:40 +01:00
Robert Jördens 37f9c0b10c spi: register clk 
following m-labs/misoc#65
1dc68b0d0b
 2017-12-28 16:50:22 +01:00
whitequark acd13837ff firmware: implement the new bootloader. 2017-12-28 13:18:51 +00:00
Sebastien Bourdeauducq 8153cfa88f drtio/gth: add probes on {tx,rx}_init.done 2017-12-28 16:49:08 +08:00
Sebastien Bourdeauducq c086149782 drtio/gth: use async microscope probes 2017-12-28 16:37:40 +08:00
whitequark d94db1de5d Revert accidentally committed parts of 1b9b5602. 2017-12-28 08:23:34 +00:00
whitequark 1b9b560242 firmware: use libbuild_misoc in libdrtioaux. NFC. 2017-12-28 08:20:23 +00:00
Sebastien Bourdeauducq 6801921fc0 drtio: instrument GTH transceiver 2017-12-28 15:03:14 +08:00
Sebastien Bourdeauducq 70b7f28ad3 drtio: drive SFP TX disable pins 2017-12-23 22:58:51 +08:00
Sebastien Bourdeauducq f8c8f3fe26 drtio: fix GTH clock domains 2017-12-23 07:21:44 +08:00
Sebastien Bourdeauducq 1af21c0b29 drtio: integrate GTH transceiver for Sayma 2017-12-23 01:19:59 +08:00
Sebastien Bourdeauducq c57b66497c drtio: refactor/simplify GTH, use migen 2017-12-23 01:19:44 +08:00
Sebastien Bourdeauducq 77897228ca drtio: add GTH transceiver code from Florent (197c79d47) 2017-12-22 18:01:28 +08:00
Sebastien Bourdeauducq ebdbaaad32 drtio: remove KC705/GTX support 2017-12-22 17:51:42 +08:00
Sebastien Bourdeauducq 0681d472c7 conda: fix sayma_rtm_csr.csv location for Sayma AMC 2017-12-22 17:14:10 +08:00
Sebastien Bourdeauducq 44959144d8 conda: add Sayma AMC standalone board package 2017-12-22 16:44:04 +08:00
Florent Kermarrec 86825a852c gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200 2017-12-21 23:52:44 +01:00
Sebastien Bourdeauducq a6ffe9f38d drtio: add Sayma top-level designs 2017-12-21 23:08:56 +08:00
Sebastien Bourdeauducq 4fbc8772a5 sayma: allocate all user LEDs to RTIO, make one TTL SMA input 2017-12-21 19:27:38 +08:00
Sebastien Bourdeauducq a23251276d Revert "sayma: set up Si5324 for RGMII clock rerouting" 
This reverts commit 2b01aa22b6.
 2017-12-21 14:42:15 +08:00
Sebastien Bourdeauducq 2b01aa22b6 sayma: set up Si5324 for RGMII clock rerouting 2017-12-17 00:25:33 +08:00
Sebastien Bourdeauducq b6199bb35b sayma: style 2017-12-15 19:45:51 +08:00
Sebastien Bourdeauducq 649b60ea29 targets/kc705_drtio: remove DAC FMC card support 2017-12-15 17:32:25 +08:00
Sebastien Bourdeauducq 341e809859 targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator 2017-12-15 13:08:35 +08:00
Sebastien Bourdeauducq 569484f888 remove phaser, adapt SAWG example to Sayma 2017-12-14 18:49:27 +08:00
Robert Jördens 5e251cd85c sayma_amc: remove redundant bitstream options 
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
 2017-12-13 14:39:32 +01:00
Robert Jördens a9d0f253a5 sayma_amc: set bitstream and config parameters 
* slow down CCLK rate as there is additional loading
  on the signals
* single bit SPI for now until we know that quad SPI
  works
* set up

https://github.com/m-labs/artiq/issues/847
 2017-12-13 21:21:52 +08:00
whitequark 1c25f7ef52 gateware: make software builds spew less junk on the console. 
[ci skip]
 2017-12-04 14:19:35 +00:00
Sebastien Bourdeauducq bb3d6ef84a sayma: remove ad9154 from mem_map 
Address is autogenerated by CSR system.
 2017-11-29 18:17:25 +08:00
Robert Jördens ecfe2e40ee sayma_amc_standalone: rtio channels for both sawg groups 2017-11-19 18:32:42 +01:00
Robert Jördens d1a7c1c3a1 sayma_amc_standalone: connect sawg to jesd again 2017-11-19 14:36:20 +01:00
Florent Kermarrec dfdd2dd9e6 gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb 2017-11-19 09:01:20 +01:00
Florent Kermarrec cd83b71d92 gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping 2017-11-18 18:10:28 +01:00
Florent Kermarrec f003566e52 serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue... 
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
 2017-11-18 18:01:46 +01:00
Florent Kermarrec 1b976bfa4d gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x 2017-11-18 17:57:11 +01:00
Florent Kermarrec 464b24a608 gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints. 2017-11-10 10:48:32 +01:00
Florent Kermarrec 278c739d30 gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints 2017-11-10 10:39:47 +01:00
Florent Kermarrec 48bfaec8d3 gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8 2017-11-10 10:37:08 +01:00
Florent Kermarrec 59be095512 gateware/serwb/kusphy: use locally inverted clk_b on iserdese3 2017-11-10 10:35:48 +01:00
Florent Kermarrec db82b11f29 gateware/serwb/core: cleanup and increase fifo depth 2017-11-10 10:33:39 +01:00
Florent Kermarrec 76ddb063cf gateware/targets/sayma: get hmc830/7043 spi working (still need to test clock generation) 2017-11-06 12:08:28 +01:00
Florent Kermarrec 5bd1e43ced gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
Sebastien Bourdeauducq d80cf8d59d kc705: add TTLs and shift register driver for FMC DIO 2017-10-31 23:14:39 +08:00
Sebastien Bourdeauducq d5b5076f67 gateware/ad5360_monitor: fix SPI data decoding 2017-10-26 11:58:59 +08:00
Sebastien Bourdeauducq 412548a86c gateware: add AD5360 monitor (untested) 2017-10-23 20:09:28 +08:00
Sebastien Bourdeauducq 5803ac9998 gateware: add Zotino SPI to NIST CLOCK target 2017-10-23 15:04:30 +08:00
Sebastien Bourdeauducq 4fa823b62a gateware: add support for SPI-over-LVDS 2017-10-23 15:04:01 +08:00
Sebastien Bourdeauducq 893be82ad1 rtio/dma: raise underflow in test 2017-10-09 10:22:58 +08:00
Sebastien Bourdeauducq a9c9d5779d rtio/dma: add full-stack test with connection to RTIO core 2017-10-08 22:38:02 +08:00
Sebastien Bourdeauducq 5f083f21a4 rtio/dma: fix signal width 2017-10-08 22:37:46 +08:00
Robert Jördens c7de233208 Merge Sayma SAWG changes (untested) 
See #798

* sinara:
  conda: bump migen
  sayma_amc: SAWG (untested)
  sayma_rtm: make build dir
  conda: jesd204b 0.4
 2017-09-29 21:01:02 +02:00
Sebastien Bourdeauducq b4c52c34f7 Merge branch 'sinara' 2017-09-30 01:11:16 +08:00
Sebastien Bourdeauducq 6c049ad40c rtio: report channel numbers in asynchronous errors 2017-09-29 16:32:57 +08:00
Sebastien Bourdeauducq 5437f0e3e3 rtio: make sequence errors consistently asychronous 2017-09-29 14:40:06 +08:00
Robert Jördens 5e3cc83842 sayma_amc: SAWG (untested) 2017-09-27 18:44:35 +02:00
Robert Jördens 2604806512 sayma_rtm: make build dir 2017-09-27 18:35:46 +02:00
Sebastien Bourdeauducq 73043c3464 drtio: disable SED lane spread 
Doesn't improve things as the buffer space would still be determined
by the full FIFO, and adds unnecessary logic.
 2017-09-26 16:46:09 +08:00
Sebastien Bourdeauducq d7ef07a0c2 rtio/sed: document architecture 2017-09-26 16:44:23 +08:00
Sebastien Bourdeauducq e6f0ce3aba rtio/sed: test latency compensation 2017-09-26 16:11:21 +08:00
Sebastien Bourdeauducq 9905b8723b rtio/sed: support negative latency compensation 2017-09-26 16:11:08 +08:00
Sebastien Bourdeauducq f079ac6af6 rtio/sed: disable wait in TestLaneDistributor.test_regular 2017-09-26 16:10:52 +08:00
Sebastien Bourdeauducq 4112e403de rtio/sed: latency compensation 2017-09-26 15:09:07 +08:00
Sebastien Bourdeauducq e430d04d3f drtio: remove obsolete import 2017-09-24 12:49:21 +08:00
Sebastien Bourdeauducq 20d79c930c drtio: use SED and input collector 2017-09-24 12:23:47 +08:00
Sebastien Bourdeauducq aa8fc81a87 rtio: allow specifying glbl_fine_ts_width externally 2017-09-23 22:34:55 +08:00
Sebastien Bourdeauducq 5cf0693758 rtio: use BlindTransfer to report collision and busy errors to sys domain 2017-09-21 22:31:56 +08:00
Sebastien Bourdeauducq d74a7d272e rtio: fix/cleanup parameters 2017-09-21 15:59:48 +08:00
Sebastien Bourdeauducq 07d3f87c51 rtio/sed: min_space → buffer_space 2017-09-21 14:36:13 +08:00
Sebastien Bourdeauducq d8aa75b742 rtio/sed: add minimum buffer space reporting 2017-09-20 11:27:57 +08:00
Sebastien Bourdeauducq 63e39dec94 style 2017-09-20 11:26:12 +08:00
Sebastien Bourdeauducq 9ccd95e10d drtio: remove spurious signals 2017-09-19 20:48:12 +08:00
Sebastien Bourdeauducq 7249f151a5 targets/kc705_drtio_satellite: add missing shebang line 2017-09-19 20:48:12 +08:00
Sebastien Bourdeauducq 171a2d19a0 drtio: remove spurious signals 2017-09-19 20:47:37 +08:00
Sebastien Bourdeauducq 1ff10785dc targets/kc705_drtio_satellite: add missing shebang line 2017-09-19 20:46:16 +08:00
Sebastien Bourdeauducq ddcd6065e8 rtio: drive InputCollector.coarse_timestamp 2017-09-19 17:46:38 +08:00
Sebastien Bourdeauducq ff8e17ab89 rtio: use input collector module 2017-09-19 15:53:35 +08:00
Sebastien Bourdeauducq 4dc80e3d05 rtio: add missing import 2017-09-19 15:53:23 +08:00
Sebastien Bourdeauducq 06a0707c00 rtio: add simulation unit test for input collector 2017-09-19 15:30:44 +08:00
Sebastien Bourdeauducq d37577a8a1 rtio: add input collector module 2017-09-19 15:30:30 +08:00
Sebastien Bourdeauducq 6dc9cad2c9 rtio: add explanation about cri.counter 2017-09-19 12:05:12 +08:00
Sebastien Bourdeauducq 81d6317053 rtio/sed: take global fine TS width 2017-09-18 11:30:49 +08:00
Sebastien Bourdeauducq 65baca8c57 rtio: clean up error-prone rtlink.get_or_zero() 2017-09-17 16:11:36 +08:00
Sebastien Bourdeauducq 0824e0aeae gateware/targets: remove deprecated ofifo_depth parameter 2017-09-16 17:04:11 +08:00
Sebastien Bourdeauducq e2c1d4f3d5 rtio/sed: trigger collision error on non-data replace 2017-09-16 17:01:23 +08:00
Sebastien Bourdeauducq 0e25154e25 rtio/sed: quash writes to LogChannel 2017-09-16 15:19:30 +08:00
Sebastien Bourdeauducq 1cfe90b1d9 rtio/sed/Gates: fix fine_ts_width computation 2017-09-16 15:09:21 +08:00
Sebastien Bourdeauducq 30e7765a2e drtio: add missing import 2017-09-16 14:36:27 +08:00
Sebastien Bourdeauducq a3bb6c167c rtio: use SED 2017-09-16 14:13:42 +08:00
Sebastien Bourdeauducq 131f5e4a3b rtio/sed/LaneDistributor: fix CRI address 2017-09-16 14:13:01 +08:00
Sebastien Bourdeauducq 25c644c663 rtio/sed: add top-level core unit test 2017-09-16 14:05:08 +08:00
Sebastien Bourdeauducq a155a481b1 rtio/sed: add top-level core 2017-09-16 14:04:56 +08:00
Sebastien Bourdeauducq 92c63ce2e4 rtio/sed: rename fifos/gates, refactor tsc 2017-09-16 14:03:48 +08:00
Sebastien Bourdeauducq ac52c7c818 rtio/sed/LaneDistributor: style 2017-09-16 14:02:37 +08:00
Sebastien Bourdeauducq 7b299ba583 rtio/sed: remove obsolete ofifo_depth from test_output_driver 2017-09-16 14:01:19 +08:00
Sebastien Bourdeauducq 6b7a1893c7 rtio/sed/OutputDriver: support channels with different fine timestamp widths 2017-09-16 10:53:30 +08:00
Sebastien Bourdeauducq f39ee7ad62 rtio/sed: fix seqn_width 2017-09-16 10:52:37 +08:00
Sebastien Bourdeauducq 064503f224 rtio/sed/LaneDistributor: support specifying existing CRI 2017-09-16 10:52:13 +08:00
Sebastien Bourdeauducq 1cb05f3ed5 rtio/sed/LaneDistributor: persist underflow/sequence error until next write 2017-09-16 10:51:44 +08:00
Sebastien Bourdeauducq 3c922463a0 style 2017-09-15 15:36:46 +08:00
Sebastien Bourdeauducq 8e5ab90129 rtio/sed: add FIFO wrapper 2017-09-15 15:36:34 +08:00
Sebastien Bourdeauducq 490c9815a2 rtio/sed: add TSC/gate (untested) 2017-09-14 19:53:21 +08:00
Sebastien Bourdeauducq 181cb42ba8 rtio/sed: centralize all layouts in one file 2017-09-14 19:52:31 +08:00
Sebastien Bourdeauducq 1b61442bc3 rtio/sed: fix lane spreading and enable by default 2017-09-13 22:48:10 +08:00
Sebastien Bourdeauducq 8cfe2ec53a rtio/sed: fix sequence number width computation 2017-09-13 22:11:41 +08:00
Sebastien Bourdeauducq a92a955d1e rtio/sed: use __all__ 2017-09-13 18:17:22 +08:00
Sebastien Bourdeauducq feec6298a5 rtio/sed: add lane distributor simulation unittest 2017-09-13 18:00:16 +08:00
Sebastien Bourdeauducq c74abccfd5 rtio/sed: lane distributor fixes 2017-09-13 17:50:06 +08:00
Sebastien Bourdeauducq bdd96084c5 rtio/sed: add lane distributor (untested) 2017-09-13 00:07:26 +08:00
Sebastien Bourdeauducq faf54127ac rtio/sed: remove VCD fine in unittest 2017-09-11 23:07:09 +08:00
Sebastien Bourdeauducq a2b7894134 rtio/sed: add output driver simulation unittest 2017-09-11 23:05:10 +08:00
Sebastien Bourdeauducq 00ff3f5b0d rtio/sed: fix output driver busy output 2017-09-11 23:04:52 +08:00
Sebastien Bourdeauducq 64d9381c36 rtio/sed: remove uneeded yield in test_sed_output_network 2017-09-11 23:02:56 +08:00
Sebastien Bourdeauducq 666bc600a2 rtio/sed: add output driver (untested) 2017-09-11 11:10:28 +08:00
Sebastien Bourdeauducq 1d2ebbe60f rtio/sed: make ON payload layout configurable, add latency function 2017-09-11 09:06:40 +08:00
Sebastien Bourdeauducq 527b403bb1 rtio/sed: add output network simulation unittest 2017-09-10 23:41:20 +08:00
Sebastien Bourdeauducq c5d6a2ba1a rtio/sed: more output network fixes 2017-09-10 23:41:04 +08:00
Sebastien Bourdeauducq 96505a1cd9 rtio/sed: output network fixes 2017-09-10 23:23:10 +08:00
Sebastien Bourdeauducq 5646e19dc3 rtio/sed: add output network (untested) 2017-09-10 14:38:43 +08:00
Florent Kermarrec 2091c7696a artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode 2017-09-06 09:18:12 +02:00
Sebastien Bourdeauducq 9edff2c520 remote_csr: interpret length as CSR size, not number of bus words 2017-08-31 13:34:48 +08:00
Sebastien Bourdeauducq 0a5904bbaa firmware: support for multiple JESD DACs 2017-08-31 13:05:48 +08:00
Sebastien Bourdeauducq a4144a07c4 sayma_amc: add converter SPI config defines 2017-08-31 13:04:38 +08:00
Sebastien Bourdeauducq bacf8a1614 style 2017-08-31 12:52:09 +08:00
Sebastien Bourdeauducq ad0a940e2d sayma_rtm: hook up DAC SPI 2017-08-31 11:48:54 +08:00
Sebastien Bourdeauducq f765dc50de sayma_rtm: do not keep DACs in reset 2017-08-31 11:44:33 +08:00
Sebastien Bourdeauducq a67659338d sayma: clean up serwb comments 2017-08-31 11:42:01 +08:00
Florent Kermarrec 660f9856ec gateware/serwb: add test for phy initialization 2017-08-30 17:59:10 +02:00
Florent Kermarrec 9650233007 gateware/serwb: change serdes clock domain to serwb_serdes 2017-08-30 15:44:44 +02:00
Florent Kermarrec 32ca51faee gateware/targets/sayma_amc_standalone/rtm: use new serwb modules 2017-08-30 15:25:20 +02:00
Florent Kermarrec 41d57d64f6 gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
Florent Kermarrec 9ba50098a8 gateware/test/serwb: use unittest for in test_etherbone 2017-08-29 17:31:01 +02:00
Florent Kermarrec 7d7f6be7ce gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction 2017-08-29 16:41:29 +02:00
Florent Kermarrec 60ad36e7d6 gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready 2017-08-29 13:43:26 +02:00
Florent Kermarrec 89558e2653 gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors 
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
 2017-08-29 13:38:52 +02:00
Sebastien Bourdeauducq 26a11a296c sayma_rtm: drive DAC control signals 2017-08-26 16:57:02 -07:00
Sebastien Bourdeauducq d609c67cbd sayma_rtm: set clock mux pins 2017-08-26 16:48:10 -07:00
Sebastien Bourdeauducq 9194402ea5 sayma_rtm: expose HMC SPI bus 2017-08-26 16:31:31 -07:00
Sebastien Bourdeauducq dbc12540da sayma_amc: register RTM CSR regions from CSV 2017-08-26 14:48:11 -07:00
Sebastien Bourdeauducq 54c75d3274 sayma_rtm: use CSR infrastructure, generate CSR CSV 2017-08-23 17:19:53 -04:00
Sebastien Bourdeauducq 668450db26 sayma_amc: add serwb 2017-08-21 18:11:29 -04:00
Sebastien Bourdeauducq 0459a70cf6 sayma_amc: cleanup, fix RTM UART forwarding 2017-08-21 16:49:42 -04:00
Sebastien Bourdeauducq 1f2b373d09 sayma_rtm: remove unnecessary serwb_control 2017-08-21 16:37:13 -04:00
Sebastien Bourdeauducq bfea297279 targets: add Sayma RTM 2017-08-21 15:58:01 -04:00
Sebastien Bourdeauducq 53c7f92fdc serwb: add __init__.py and expose submodules 2017-08-21 15:57:43 -04:00
Sebastien Bourdeauducq dac3a78b75 serwb: style, use migen, fix imports 2017-08-21 12:35:59 -04:00
Florent Kermarrec da90a0fa12 Add test for Etherbone 
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
 2017-08-21 12:31:49 -04:00
Florent Kermarrec 44dc76e42e Add serial Wishbone bridge 
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
 2017-08-21 12:22:05 -04:00
Sebastien Bourdeauducq d6b624dfbe sayma_amc: connect RTM serial and second serial 2017-08-20 19:01:55 -04:00
Sebastien Bourdeauducq bee4902323 add Sayma AMC standalone target 2017-08-20 11:47:45 -04:00
Sebastien Bourdeauducq 1dab7df846 kc705_sma_spi: fix permissions 2017-08-20 10:54:24 -04:00
Sebastien Bourdeauducq df4f38a1e4 kc705: add pullup on SD card MISO 2017-07-24 22:26:16 +08:00
Sebastien Bourdeauducq a201a9abd9 drtio: multilink transceiver interface 2017-07-18 13:27:33 +08:00
Sebastien Bourdeauducq 9045b4cc19 drtio: initial firmware support for multi-link 2017-07-18 00:40:21 +08:00
Sebastien Bourdeauducq 4deb5f6a45 gateware: use new MiSoC Wishbone address system 2017-07-13 19:16:49 +08:00
mntng 40ca951750 kc705: add SPI bus for memory card 
This will be useful for SPI unit tests using a SD card as victim.
 2017-07-12 00:27:44 +08:00
Robert Jördens 7b130a2c32 sawg: confirm smooth(order=3) 2017-07-07 11:36:03 +02:00
Robert Jördens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" 
This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
 2017-07-04 17:55:19 +02:00
Robert Jördens 8e0a1cbdc8 sawg: advance dds 1/2 by one sample group 
closes #772
 2017-07-04 16:51:58 +02:00
Robert Jördens 91ca9fbcad sawg: also give offset some headroom 
closes #771
 2017-07-04 16:50:06 +02:00
Robert Jördens 78d1f0fdf6 sawg: fix PhasedAccu resets 2017-07-04 11:56:21 +02:00
Florent Kermarrec 2910b1be5e artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect 2017-07-04 10:48:06 +02:00
Sebastien Bourdeauducq 838127d914 rtio: break DMA timing path 2017-07-02 10:24:01 +08:00
Robert Jördens 911ee4a959 rtio: make pipelined logic reset_less 
* latency-corrected counters
* registered error logic
 2017-06-29 12:55:32 +02:00
Robert Jördens 600a48ac61 dsp.fir: cleanup 2017-06-29 12:18:48 +02:00
Robert Jördens dca662a743 dsp.fir: pipeline final systolic adder 2017-06-29 11:33:19 +02:00
Robert Jördens 32a33500c8 dsp.fir: actively cull zero delays 2017-06-29 11:24:56 +02:00
Robert Jördens f520d4a768 rtio: undo _RelaxedAsyncResetSynchronizer 2017-06-28 22:08:15 +02:00
Robert Jördens 3cbbcdfe96 sawg: don't enable_replace for Config 
closes #762
 2017-06-28 20:31:40 +02:00
Robert Jördens f2632e0fd1 sawg: adapt latency to fir changes 
closes #748
 2017-06-28 20:12:30 +02:00
Robert Jördens e7db2c6578 dsp.accu: reset_less outputs 2017-06-28 20:04:58 +02:00
Robert Jördens 6bb994228f dsp.fir: drop x shift 2017-06-28 19:55:15 +02:00
Robert Jördens 01847271c5 rtio: use reset_less signal for reset fanout 2017-06-28 19:43:55 +02:00
Robert Jördens b9859cc0c3 dsp.fir: remove old/wrong comment 2017-06-28 19:21:57 +02:00
Robert Jördens 55b5b87490 fir: simplify latency compensation 
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
 2017-06-28 19:13:43 +02:00
Robert Jördens d1e5dd334f sawg: use pipeline reset 2017-06-28 19:09:39 +02:00
Robert Jördens 6418205906 dsp.fir: use pipelin-reset 2017-06-28 19:09:21 +02:00
Robert Jördens 07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
Robert Jördens f78d5a87e9 dsp/test: skip and fix sat_add 2017-06-22 18:01:31 +02:00
Robert Jördens 47928a2c0d sawg: disable limiter 
temporary workaround to permit testing other aspects
 2017-06-22 17:31:04 +02:00
Robert Jördens cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
Robert Jördens 9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
Robert Jördens d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
Robert Jördens 694f8d784c dsp/tools: unittest sat_add 2017-06-22 11:29:56 +02:00
Robert Jördens bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
Robert Jördens cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
Robert Jördens 5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
Robert Jördens 570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
Robert Jördens 4b3aad2563 sawg: clean up Config 
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
 2017-06-22 10:26:29 +02:00
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Robert Jördens ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
Robert Jördens b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
Sebastien Bourdeauducq 74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
Robert Jördens 0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
Robert Jördens 424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
Robert Jördens 219dfd8984 rtio: add one register level for rio and rio_phy resets 
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
 2017-06-17 12:17:48 +02:00
Robert Jördens e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
Robert Jördens 2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
Robert Jördens 3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
Robert Jördens e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
Robert Jördens 315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
Robert Jördens 9a8a7b9102 sawg: handle clipping interpolator 
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
 2017-06-12 20:33:54 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens bfc224d4ba phaser: adjust to new jesd 2017-05-22 19:59:53 +02:00
Robert Jördens 679060af1d phaser: enable dma 2017-05-22 19:32:34 +02:00
Robert Jördens 4901cb9a8a sawg: fix clr width 2017-05-22 17:46:55 +02:00
Robert Jördens 253ee950f6 sawg: fix config channel addr 2017-05-22 17:45:14 +02:00
Sebastien Bourdeauducq 9ab63920e0 Remove Pipistrello support 
Closes #658
Closes #381
 2017-05-15 17:17:44 +08:00
Robert Jördens 170d2886fd Merge branch 'pdq' 
* pdq:
  pdq: documentation
  pdq2 -> pdq
  pdq2: use 16 bit data, buffered read_mem()
  spi: style
  pdq2: mem_read
  pdq2: align subsequent writes to end
  sma_spi: undo cri_con
  pdq2: memory write, kernel_invariants
  sma_spi: cri/cd changes
  sma_spi: LVCMOS25
  coredevice.spi: kernel invariants and style
  sma_spi: free up user_sma pins
  sma_spi: add demo target with SPI on four SMA
  pdq2: memory write
  pdq2: crc/frame register accessors
  doc: pdq2 spi backend
  pdq2: config writes
 2017-05-12 11:46:45 +02:00
Florent Kermarrec 79c339d4ac gateware/targets/phaser: jesd core now handles jsync completely 2017-04-26 22:25:08 +02:00
Florent Kermarrec 0546affd4c gateware/target/phaser: jesd start signal renamed to jsync 2017-04-26 12:27:40 +02:00