f8e6b4f4e3
ad5360: port to spi2
...
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
fa0d929b4d
drtio: reorganize RX synchronizers
2018-02-22 15:21:23 +08:00
e5de5ef473
kasli: use deterministic RX synchronizer
...
Could not reproduce the "fully broken bitstream" bug.
2018-02-22 15:18:09 +08:00
a5ad1dc266
kc705: fix sdcard miso pullup
2018-02-21 19:41:05 +01:00
0d8145084d
test_spi: move to new spi2 core
2018-02-21 19:41:05 +01:00
a63fd306af
urukul: use spi2
...
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
2018-02-21 15:00:28 +00:00
37a0d6580b
spi2: add RTIO gateware and coredevice driver
...
1006218997
2018-02-21 13:37:36 +00:00
91a4a7b0ee
kasli: free run si5324 on opticlock for now
2018-02-21 13:37:29 +00:00
7a1d71502a
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
2018-02-21 13:37:29 +00:00
476e4fdd56
ttl_serdes_7series: disable IBUF and INTERM when output
2018-02-21 13:37:29 +00:00
f060d6e1b3
drtio: increase A7 clock aligner check period
2018-02-20 18:50:35 +08:00
f15b4bdde7
style
2018-02-20 18:47:59 +08:00
7d9c7ada71
drtio: fix test infinite loop
2018-02-20 17:42:00 +08:00
ad2c9590d0
drtio: rewrite/fix reset and link bringup/teardown
2018-02-20 17:26:43 +08:00
7e02d8245c
kasli: false paths
...
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
0f4549655b
sayma: use Xilinx RX synchronizer
...
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
2018-02-19 17:49:53 +08:00
52049cf36a
drtio: add Xilinx RX synchronizer
2018-02-19 17:49:43 +08:00
3bc575bee7
drtio: add missing define for Sayma master
2018-02-19 17:11:21 +08:00
7376ab0ff8
drtio: fix Sayma after 83abdd28
2018-02-19 17:10:55 +08:00
Florent Kermarrec
f5831af535
drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
2018-02-19 10:03:19 +01:00
Florent Kermarrec
89a158c0c9
drtio/transceiver/gtp_7series_init: remove dead code
2018-02-19 10:02:23 +01:00
Florent Kermarrec
782051f474
drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
2018-02-19 09:59:50 +01:00
c329c83676
kasli: fix disable_si5324_ibuf no_retiming
2018-02-19 12:19:05 +08:00
a93decdef2
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
2018-02-19 00:48:37 +08:00
94c20dfd4d
drtio: fix misleading GenericRXSynchronizer comment
2018-02-19 00:47:54 +08:00
83abdd283a
drtio: signal stable clock input to transceiver
2018-02-18 22:29:30 +08:00
287d533437
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908 "
...
This reverts commit 2d4a1340ea
2018-02-17 17:38:48 +08:00
73985a9215
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
2018-02-17 17:38:17 +08:00
039dee4c8e
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
...
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
2018-02-17 13:54:50 +08:00
cfb21ca126
si5324: fix usage of external CLKIN2 reference
2018-02-17 13:52:01 +08:00
e41f49cc75
kasli: opticlock 125 MHz, mark external reference case broken
2018-02-16 17:23:15 +00:00
4d42df2a7c
kasli: set up Si5324 in standalone operation
2018-02-15 20:32:58 +08:00
d7387611c0
sayma: print RTM gateware version
2018-02-15 19:31:58 +08:00
be693bc8a9
opticlock: examples
2018-02-13 22:13:40 +01:00
a3d136d30d
opticlock: wire urukul and novogorny
2018-02-13 22:13:40 +01:00
ab5f397fea
sed/fifos: use AsyncFIFOBuffered
...
(D)RTIO now passes timing at 150MHz on Kasli.
2018-02-13 20:02:51 +08:00
00f42f912b
rename 'RTM identifier' to 'RTM magic number'
...
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
2018-02-13 20:02:51 +08:00
96b948f57f
remote_csr: add sanity check of CSR CSV type column
2018-02-13 20:02:51 +08:00
Florent Kermarrec
bfdda340fd
drtio/transceiver/gtp_7series: use parameters from xilinx wizard
2018-02-13 00:23:59 +01:00
Florent Kermarrec
180c28551d
drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable)
2018-02-09 20:17:02 +01:00
2d4a1340ea
sayma_amc: remove RTM bitstream upload core. Closes #908
2018-02-07 12:27:35 +08:00
whitequark
61c64a76be
gateware: use a per-variant subfolder in --output-dir. ( fixes #912 )
...
This commit also adds support for --variant and --args
to artiq-devtool.
2018-02-06 08:19:01 +00:00
whitequark
885ab40946
conda: split RTM and AMC packages back.
...
This avoids multiplying the RTM compilation time by the number
of AMC packages.
2018-01-28 14:27:55 +00:00
whitequark
11a8b84355
Merge the build trees of sayma_amc and sayma_rtm targets.
...
This also makes them a single artiq_flash target, and a single
conda package.
2018-01-27 19:54:31 +00:00
440e19b8f9
kasli: use SFP2 for DRTIO mastering
...
SFP1 PCB routing has some issues.
Also use SFP1 LED for DRTIO in both master and satellite.
2018-01-26 19:02:54 +08:00
e0e795f11c
sayma_amc: constrain pin, remove keep
2018-01-23 15:42:47 +00:00
b5c035bb52
sayma_rtm: constrain serwb clock input
2018-01-23 13:54:53 +00:00
aada38f508
kasli, kc705: remove vivado "keep", cleanup a constraint
2018-01-23 13:15:26 +00:00
85102e191e
sayma_rtm: derive clocks automatically
...
* also don't add false paths unless necessary
2018-01-23 11:00:55 +00:00
7d1b3f37c9
sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
2018-01-23 10:56:42 +00:00
649deccd9b
kasli: fix DRTIO satellite QPLL refclksel
2018-01-23 12:27:19 +08:00
4b4374f76a
sayma: register_jref for JESD204. Closes #904
2018-01-23 12:19:15 +08:00
763aefacff
kasli: fix typo
2018-01-23 12:10:54 +08:00
c7b148a704
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
2018-01-23 12:08:10 +08:00
d6157514c7
gtp_7series: flexible QPLL channel selection
2018-01-23 12:03:09 +08:00
9f87c34a94
kasli: fix QPLL instantiation
2018-01-23 10:39:31 +08:00
98a5607634
gtp_7series: set clock muxes correctly for second QPLL channel
2018-01-23 10:39:20 +08:00
25fee1a0bb
gtp_7series: use QPLL second channel
2018-01-23 10:15:49 +08:00
031d7ff020
kasli: keep using second QPLL channel for DRTIO satellite
2018-01-23 10:13:10 +08:00
626075cbc1
gtp_7series: simplify TX clocking
2018-01-23 09:49:23 +08:00
401e57d41c
gtp_7series: fix nchannels assert
2018-01-23 01:28:01 +08:00
aa62e91487
kasli: add DRTIO targets (no firmware)
2018-01-23 01:27:40 +08:00
296ac35f5d
sayma_amc: SFP TX disable is active-high
2018-01-23 00:32:09 +08:00
77192256ea
kc705: style
2018-01-23 00:02:35 +08:00
ab7c49d6d0
sayma_amc: raise error on invalid variant
2018-01-23 00:02:16 +08:00
c1ac3b66b1
sayma_rtm: fix 8fe463d4a
2018-01-23 00:01:45 +08:00
53facfef13
sayma: build fixes
2018-01-22 18:33:22 +08:00
25f3feeda8
refactor targets
2018-01-22 18:25:10 +08:00
5198c224a2
sayma,kasli: use new pin names
2018-01-22 11:51:07 +08:00
Florent Kermarrec
8fe463d4a0
sayma_rtm: add UART loopback to easily know if rtm fpga is alive
2018-01-20 06:04:34 +01:00
Florent Kermarrec
74ce7319d3
sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?)
2018-01-20 06:04:18 +01:00
Florent Kermarrec
d27727968c
add artix7 gtp (3gbps), share clock aligner with gth_ultrascale
2018-01-19 12:17:54 +01:00
cdbf95d46a
kasli: fix permissions
2018-01-19 18:31:20 +08:00
8ec33ae7bd
kasli: feed EEM clock fan-out from SI5324
2018-01-17 17:27:59 +01:00
ed3e3b2791
sayma_amc: clarify --with-sawg help
2018-01-17 12:10:30 +01:00
Florent Kermarrec
f54b27b79c
sayma_amc: prepare for jesd subclass 1
2018-01-17 11:49:36 +01:00
Florent Kermarrec
f73c3e5944
gateware/test/serwb: update and cleanup test (v2...)
2018-01-16 20:06:43 +01:00
7405006668
sayma: rtio clock is jesd fabric clock
2018-01-16 18:19:04 +01:00
whitequark
247167d34a
Revert "gateware/test/serwb: update and cleanup tests"
...
This reverts commit 5b03cc2fae
2018-01-16 08:21:26 +00:00
whitequark
444b901dbe
sayma: add RTM configuration port.
2018-01-16 07:28:00 +00:00
Florent Kermarrec
5b03cc2fae
gateware/test/serwb: update and cleanup tests
2018-01-15 21:53:40 +01:00
whitequark
6891141fa6
artiq_flash: add sayma support.
2018-01-15 11:43:29 +00:00
529033e016
kernel_cpu: disable PCU
...
* contributes to long timing paths on artix 7 (kasli)
* currently only used for testing and debugging
2018-01-12 12:03:50 +00:00
ac3c3871d0
kasli: s/extensions/variant/g
2018-01-12 12:29:42 +01:00
7c82fcf41a
targets: avoid passing cpu_type around unnecessarily
2018-01-11 11:21:55 +08:00
6d58c4390b
Merge branch 'sed-merge'
2018-01-10 13:14:39 +08:00
04b2fd3e13
sayma: fix AD9154NoSAWG ramp clock domain
2018-01-10 12:11:33 +08:00
dc593ec0f0
Merge branch 'rtio-sed' into sed-merge
2018-01-10 12:04:54 +08:00
Florent Kermarrec
2009734b3c
serwb/phy: get 625Mbps linerate working, increase timeout
2018-01-09 18:54:52 +01:00
Florent Kermarrec
9c6a7f7509
serwb/kusphy: use same serwb_serdes_5x reset than s7phy
2018-01-09 18:54:05 +01:00
8813aee6b1
targets: add kasli [wip, untested]
2018-01-04 16:12:12 +01:00
Florent Kermarrec
1e972034e8
gateware/targets: enable serwb scrambling on sayma amc & rtm
2018-01-03 17:34:46 +01:00
Florent Kermarrec
907af25a69
gateware/serwb: add scrambling, reduce cdc fifo depth
2018-01-03 17:34:03 +01:00
Florent Kermarrec
7f4756a869
gateware/serwb: cleanup packet
2018-01-03 17:30:12 +01:00
c2be820e9a
kc705_dds: make ext_clkout 100 MHz
2018-01-02 19:58:47 +01:00
43686f324b
kc705_dds: fix HPC voltages
...
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V
* the direction control register on HPC (FMC-DIO to VHDCI)
was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
and hope for the best.
2018-01-02 13:41:07 +01:00
94b84ebe7c
kc705_dds: add urukul spi/ttl channels
2018-01-02 13:20:48 +01:00
53969d3686
kc705_dds: add urukul on vhdci extension definition
2018-01-02 13:20:47 +01:00
2f8e6c7462
spi: add diff_term, save power on outputs
2018-01-02 13:20:47 +01:00
6d20b71dde
ttl_serdes_7series: refactor IOSERDES
2018-01-02 13:20:47 +01:00
745e695b09
sayma: output a ramp in the absence of SAWG channels
2017-12-31 12:18:53 +01:00
whitequark
a371b25525
bootloader: allow using without Ethernet.
2017-12-31 09:21:28 +00:00
6e0288e568
drtio: fix GTH CPLL reset
2017-12-30 12:14:36 +08:00
379d29561b
sayma: plausibility assertion on sawg data stream
2017-12-29 19:15:40 +01:00
37f9c0b10c
spi: register clk
...
following m-labs/misoc#65
1dc68b0d0b
2017-12-28 16:50:22 +01:00
whitequark
acd13837ff
firmware: implement the new bootloader.
2017-12-28 13:18:51 +00:00
8153cfa88f
drtio/gth: add probes on {tx,rx}_init.done
2017-12-28 16:49:08 +08:00
c086149782
drtio/gth: use async microscope probes
2017-12-28 16:37:40 +08:00
whitequark
d94db1de5d
Revert accidentally committed parts of 1b9b5602.
2017-12-28 08:23:34 +00:00
whitequark
1b9b560242
firmware: use libbuild_misoc in libdrtioaux. NFC.
2017-12-28 08:20:23 +00:00
6801921fc0
drtio: instrument GTH transceiver
2017-12-28 15:03:14 +08:00
70b7f28ad3
drtio: drive SFP TX disable pins
2017-12-23 22:58:51 +08:00
f8c8f3fe26
drtio: fix GTH clock domains
2017-12-23 07:21:44 +08:00
1af21c0b29
drtio: integrate GTH transceiver for Sayma
2017-12-23 01:19:59 +08:00
c57b66497c
drtio: refactor/simplify GTH, use migen
2017-12-23 01:19:44 +08:00
77897228ca
drtio: add GTH transceiver code from Florent (197c79d47)
2017-12-22 18:01:28 +08:00
ebdbaaad32
drtio: remove KC705/GTX support
2017-12-22 17:51:42 +08:00
0681d472c7
conda: fix sayma_rtm_csr.csv location for Sayma AMC
2017-12-22 17:14:10 +08:00
44959144d8
conda: add Sayma AMC standalone board package
2017-12-22 16:44:04 +08:00
Florent Kermarrec
86825a852c
gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
2017-12-21 23:52:44 +01:00
a6ffe9f38d
drtio: add Sayma top-level designs
2017-12-21 23:08:56 +08:00
4fbc8772a5
sayma: allocate all user LEDs to RTIO, make one TTL SMA input
2017-12-21 19:27:38 +08:00
a23251276d
Revert "sayma: set up Si5324 for RGMII clock rerouting"
...
This reverts commit 2b01aa22b6
2017-12-21 14:42:15 +08:00
2b01aa22b6
sayma: set up Si5324 for RGMII clock rerouting
2017-12-17 00:25:33 +08:00
b6199bb35b
sayma: style
2017-12-15 19:45:51 +08:00
649b60ea29
targets/kc705_drtio: remove DAC FMC card support
2017-12-15 17:32:25 +08:00
341e809859
targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator
2017-12-15 13:08:35 +08:00
569484f888
remove phaser, adapt SAWG example to Sayma
2017-12-14 18:49:27 +08:00
5e251cd85c
sayma_amc: remove redundant bitstream options
...
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
2017-12-13 14:39:32 +01:00
a9d0f253a5
sayma_amc: set bitstream and config parameters
...
* slow down CCLK rate as there is additional loading
on the signals
* single bit SPI for now until we know that quad SPI
works
* set up
https://github.com/m-labs/artiq/issues/847
2017-12-13 21:21:52 +08:00
whitequark
1c25f7ef52
gateware: make software builds spew less junk on the console.
...
[ci skip]
2017-12-04 14:19:35 +00:00
bb3d6ef84a
sayma: remove ad9154 from mem_map
...
Address is autogenerated by CSR system.
2017-11-29 18:17:25 +08:00
ecfe2e40ee
sayma_amc_standalone: rtio channels for both sawg groups
2017-11-19 18:32:42 +01:00
d1a7c1c3a1
sayma_amc_standalone: connect sawg to jesd again
2017-11-19 14:36:20 +01:00
Florent Kermarrec
dfdd2dd9e6
gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb
2017-11-19 09:01:20 +01:00
Florent Kermarrec
cd83b71d92
gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping
2017-11-18 18:10:28 +01:00
Florent Kermarrec
f003566e52
serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue...
...
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
2017-11-18 18:01:46 +01:00
Florent Kermarrec
1b976bfa4d
gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x
2017-11-18 17:57:11 +01:00
Florent Kermarrec
464b24a608
gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints.
2017-11-10 10:48:32 +01:00
Florent Kermarrec
278c739d30
gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints
2017-11-10 10:39:47 +01:00
Florent Kermarrec
48bfaec8d3
gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8
2017-11-10 10:37:08 +01:00
Florent Kermarrec
59be095512
gateware/serwb/kusphy: use locally inverted clk_b on iserdese3
2017-11-10 10:35:48 +01:00
Florent Kermarrec
db82b11f29
gateware/serwb/core: cleanup and increase fifo depth
2017-11-10 10:33:39 +01:00
Florent Kermarrec
76ddb063cf
gateware/targets/sayma: get hmc830/7043 spi working (still need to test clock generation)
2017-11-06 12:08:28 +01:00
Florent Kermarrec
5bd1e43ced
gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender
2017-11-03 12:15:14 +01:00
d80cf8d59d
kc705: add TTLs and shift register driver for FMC DIO
2017-10-31 23:14:39 +08:00
d5b5076f67
gateware/ad5360_monitor: fix SPI data decoding
2017-10-26 11:58:59 +08:00
412548a86c
gateware: add AD5360 monitor (untested)
2017-10-23 20:09:28 +08:00
5803ac9998
gateware: add Zotino SPI to NIST CLOCK target
2017-10-23 15:04:30 +08:00
4fa823b62a
gateware: add support for SPI-over-LVDS
2017-10-23 15:04:01 +08:00
893be82ad1
rtio/dma: raise underflow in test
2017-10-09 10:22:58 +08:00
a9c9d5779d
rtio/dma: add full-stack test with connection to RTIO core
2017-10-08 22:38:02 +08:00
5f083f21a4
rtio/dma: fix signal width
2017-10-08 22:37:46 +08:00
c7de233208
Merge Sayma SAWG changes (untested)
...
See #798
* sinara:
conda: bump migen
sayma_amc: SAWG (untested)
sayma_rtm: make build dir
conda: jesd204b 0.4
2017-09-29 21:01:02 +02:00
b4c52c34f7
Merge branch 'sinara'
2017-09-30 01:11:16 +08:00
6c049ad40c
rtio: report channel numbers in asynchronous errors
2017-09-29 16:32:57 +08:00
5437f0e3e3
rtio: make sequence errors consistently asychronous
2017-09-29 14:40:06 +08:00
5e3cc83842
sayma_amc: SAWG (untested)
2017-09-27 18:44:35 +02:00
2604806512
sayma_rtm: make build dir
2017-09-27 18:35:46 +02:00
73043c3464
drtio: disable SED lane spread
...
Doesn't improve things as the buffer space would still be determined
by the full FIFO, and adds unnecessary logic.
2017-09-26 16:46:09 +08:00
d7ef07a0c2
rtio/sed: document architecture
2017-09-26 16:44:23 +08:00
e6f0ce3aba
rtio/sed: test latency compensation
2017-09-26 16:11:21 +08:00
9905b8723b
rtio/sed: support negative latency compensation
2017-09-26 16:11:08 +08:00
f079ac6af6
rtio/sed: disable wait in TestLaneDistributor.test_regular
2017-09-26 16:10:52 +08:00
4112e403de
rtio/sed: latency compensation
2017-09-26 15:09:07 +08:00
e430d04d3f
drtio: remove obsolete import
2017-09-24 12:49:21 +08:00
20d79c930c
drtio: use SED and input collector
2017-09-24 12:23:47 +08:00
aa8fc81a87
rtio: allow specifying glbl_fine_ts_width externally
2017-09-23 22:34:55 +08:00
5cf0693758
rtio: use BlindTransfer to report collision and busy errors to sys domain
2017-09-21 22:31:56 +08:00
d74a7d272e
rtio: fix/cleanup parameters
2017-09-21 15:59:48 +08:00
07d3f87c51
rtio/sed: min_space → buffer_space
2017-09-21 14:36:13 +08:00
d8aa75b742
rtio/sed: add minimum buffer space reporting
2017-09-20 11:27:57 +08:00
63e39dec94
style
2017-09-20 11:26:12 +08:00
9ccd95e10d
drtio: remove spurious signals
2017-09-19 20:48:12 +08:00
7249f151a5
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:48:12 +08:00
171a2d19a0
drtio: remove spurious signals
2017-09-19 20:47:37 +08:00
1ff10785dc
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:46:16 +08:00
ddcd6065e8
rtio: drive InputCollector.coarse_timestamp
2017-09-19 17:46:38 +08:00
ff8e17ab89
rtio: use input collector module
2017-09-19 15:53:35 +08:00
4dc80e3d05
rtio: add missing import
2017-09-19 15:53:23 +08:00
06a0707c00
rtio: add simulation unit test for input collector
2017-09-19 15:30:44 +08:00
d37577a8a1
rtio: add input collector module
2017-09-19 15:30:30 +08:00
6dc9cad2c9
rtio: add explanation about cri.counter
2017-09-19 12:05:12 +08:00
81d6317053
rtio/sed: take global fine TS width
2017-09-18 11:30:49 +08:00
65baca8c57
rtio: clean up error-prone rtlink.get_or_zero()
2017-09-17 16:11:36 +08:00
0824e0aeae
gateware/targets: remove deprecated ofifo_depth parameter
2017-09-16 17:04:11 +08:00
e2c1d4f3d5
rtio/sed: trigger collision error on non-data replace
2017-09-16 17:01:23 +08:00
0e25154e25
rtio/sed: quash writes to LogChannel
2017-09-16 15:19:30 +08:00
1cfe90b1d9
rtio/sed/Gates: fix fine_ts_width computation
2017-09-16 15:09:21 +08:00
30e7765a2e
drtio: add missing import
2017-09-16 14:36:27 +08:00
a3bb6c167c
rtio: use SED
2017-09-16 14:13:42 +08:00
131f5e4a3b
rtio/sed/LaneDistributor: fix CRI address
2017-09-16 14:13:01 +08:00
25c644c663
rtio/sed: add top-level core unit test
2017-09-16 14:05:08 +08:00
a155a481b1
rtio/sed: add top-level core
2017-09-16 14:04:56 +08:00
92c63ce2e4
rtio/sed: rename fifos/gates, refactor tsc
2017-09-16 14:03:48 +08:00
ac52c7c818
rtio/sed/LaneDistributor: style
2017-09-16 14:02:37 +08:00
7b299ba583
rtio/sed: remove obsolete ofifo_depth from test_output_driver
2017-09-16 14:01:19 +08:00
6b7a1893c7
rtio/sed/OutputDriver: support channels with different fine timestamp widths
2017-09-16 10:53:30 +08:00
f39ee7ad62
rtio/sed: fix seqn_width
2017-09-16 10:52:37 +08:00
064503f224
rtio/sed/LaneDistributor: support specifying existing CRI
2017-09-16 10:52:13 +08:00
