0c1a76d668
unify rtio/drtio kernel interface
2016-11-01 00:30:16 +08:00
whitequark
617e345d16
gateware: fix kernel CPU exec address.
2016-10-31 15:16:35 +00:00
07ad00c1ca
drtio: split kernel/system CSRs
2016-10-31 18:09:36 +08:00
9aa94e1a2d
adapt to migen/misoc changes
2016-10-31 00:53:01 +08:00
2392113bb6
kc705: use misoc clock for false path
2016-10-30 11:16:04 +08:00
whitequark
2ac85cd40f
runtime: implement prototype background RPCs.
2016-10-29 21:34:25 +00:00
c656a53532
kc705: clean up clock constraints
2016-10-29 21:28:01 +08:00
ed4d57c638
use new Migen signal attribute API
2016-10-29 21:19:58 +08:00
da5208e160
drtio: add master gateware target
2016-10-29 17:31:15 +08:00
7c05dccf65
drtio: add support for 125MHz clock on GTX_1000BASE_BX10
2016-10-29 17:30:29 +08:00
95def81c03
drtio: squelch frame signals until link layer ready
2016-10-29 17:05:30 +08:00
4f6241283c
drtio: always use NoRetiming on MultiReg inputs
2016-10-29 16:37:53 +08:00
2a1e529dcf
phaser: DDS config dummies
2016-10-28 01:58:08 +02:00
6d07a16c62
Merge branch 'master' into phaser
...
* master: (72 commits)
gateware: extend mailbox to 3 entries.
master/worker_db: set default value for archive
master: keep dataset manager consistent when set_dataset is called with contradictory attributes
master: archive input datasets. Closes #587
master: ensure same dataset is in broadcast and local when mutating
scheduler: default submission arguments, closes #577
pdq2: sync with pdq2
doc: clarify usage of pause/check_pause, closes #571
dashboard/datasets: use scientific spinbox and increase number of decimals, closes #572
gateware/spi: fix import
runtime: fix use of $(realpath) in Makefile.
test: fix printf specifier.
llvm_ir_generator: make sure RPC allocations are not underaligned.
runtime: use i64 for watchdog timeout, not i32.
runtime: port ksupport to Rust.
runtime: remove some redundant libm functions copied inline.
language: Add "A" (ampere) as well-known unit for arguments
conda: misoc 0.4 (csr)
runtime: cap log level at debug.
runtime: discard unnecessary sections.
...
2016-10-28 01:40:11 +02:00
c428800caf
phaser: spi, sma_gpio: 2.5 V
2016-10-27 15:53:49 +02:00
65b2e4464c
phaser: sysref/sync diff term
2016-10-27 14:14:56 +02:00
ea0c304a0c
phaser2: wip
2016-10-27 01:00:42 +02:00
929a7650a8
drtio: fixes
2016-10-26 22:03:44 +08:00
45621934fd
drtio: forward errors to CSR
2016-10-26 22:03:05 +08:00
7f8e53aa5c
drtio: more fixes and tests
2016-10-26 11:48:47 +08:00
f763b519f4
drtio: fix channel selection
2016-10-26 00:33:21 +08:00
ad042de954
drtio: fixes, basic TTL working in simulation
2016-10-25 12:41:16 +08:00
e981b23548
phaser: use misoc cordic
2016-10-24 19:33:23 +02:00
d2f776b0d0
phaser: add more tools
2016-10-24 17:39:14 +02:00
a4e85081aa
drtio: more simple fixes
2016-10-24 23:32:49 +08:00
029e0d95b7
drtio: simple fixes
2016-10-24 23:10:15 +08:00
c39987b617
drtio: handle underflow/sequence error CSRs
2016-10-24 20:46:55 +08:00
7dd6eb2f5e
drtio: add RT write controller
2016-10-24 19:50:13 +08:00
83bec06226
drtio: fifo level -> fifo space
2016-10-24 15:59:12 +08:00
aa8e211735
drtio/rt_packets: fix
2016-10-22 13:03:35 +08:00
449d1c4dc6
rtio: export CDC modules
2016-10-22 13:03:10 +08:00
67c19ab178
drtio: RTPacketMaster RX, untested
2016-10-22 01:04:14 +08:00
3b4a40401a
drtio: RTPacketMaster TX (WIP)
2016-10-21 22:46:14 +08:00
1e313afe64
drtio: CrossDomainNotification
2016-10-21 22:45:45 +08:00
c71c4c89e0
drtio: change data direction in _CrossDomainRequest
2016-10-21 22:44:47 +08:00
whitequark
6872017449
gateware: extend mailbox to 3 entries.
2016-10-21 12:09:14 +00:00
6a88229e6a
drtio: CrossDomainRequest
2016-10-20 23:37:59 +08:00
9790c5d9ed
drtio/iot: FIFO level
2016-10-19 18:04:03 +08:00
71480c4d15
drtio: fix mmcm_mult
2016-10-18 17:28:03 +08:00
e7dbed3b02
gateware: KC705 satellite target
2016-10-17 19:23:45 +08:00
9752ffe3d1
drtio: various fixes
2016-10-17 19:23:08 +08:00
cce29e8b83
gateware/spi: fix import
2016-10-17 14:47:19 +08:00
b6002529cf
gateware/spi: fix import
2016-10-17 14:07:11 +08:00
85834976d9
gateware/spi: fix import
2016-10-17 14:06:35 +08:00
d3b274fc4d
drtio: synchronizer MMCM
2016-10-16 17:40:58 +08:00
03d3a85e75
drtio: RX clock alignment and ready
2016-10-15 18:36:27 +08:00
Florent Kermarrec
0259c80015
phaser/kc705: remove transceiver initialization workaround
2016-10-14 19:06:43 +02:00
d16068dd9b
sawg: absolute phase updates
2016-10-14 12:42:08 +02:00
b41b9de905
phaser: tag jesd as clock net
2016-10-14 10:46:33 +02:00
4ea3dea217
phaser: broad spectrum antibiotics with xilinx false paths
2016-10-14 10:22:03 +02:00
e400f8d672
phaser: add two more registers before jesd
2016-10-14 09:54:56 +02:00
3c9c42c779
phaser: drive rtio from jesd-bufg
2016-10-14 02:26:19 +02:00
808874a523
phaser: drive cd_jesd with BUFG
2016-10-14 01:57:48 +02:00
342d6d756e
phaser: bypass gtx phalign
2016-10-14 00:59:53 +02:00
89150c9817
phaser: 10G line rate
2016-10-14 00:53:38 +02:00
08e4aa3e3f
drtio: GTX WIP
2016-10-14 00:36:13 +08:00
c548a65ec3
drtio: clock domains
2016-10-14 00:34:59 +08:00
42c6658ffe
phaser: add some more blinking leds
2016-10-13 15:21:27 +02:00
6a456bd7d4
phaser: feed correct sink (crucial)
2016-10-13 15:17:38 +02:00
c8e45ae3f6
phaser: cleanup jesd phy instantiation a bit
2016-10-13 14:43:24 +02:00
78a41eec8f
phaser: kc705: syntax
2016-10-13 12:38:32 +02:00
Florent Kermarrec
af0e8582a2
phaser: use new jesd clocking
2016-10-13 11:51:06 +02:00
1117fe191b
phaser: support core stpl
2016-10-12 12:03:29 +02:00
f515c11f26
phaser: fix refclk period spec
2016-10-11 20:13:34 +02:00
bae5b73155
phaser: comment out stpl test
2016-10-11 19:50:19 +02:00
2b1cca2e7e
phaser: stpl
2016-10-11 19:29:27 +02:00
018f6d1b52
drtio: implement basic IOT
2016-10-11 17:59:22 +08:00
18d18b6685
phaser: add sync ttl input for monitoring
2016-10-10 17:13:23 +02:00
f5f7acc1f8
ttl_simple: add pure Input
...
(no Tristate for internal signals)
2016-10-10 17:13:23 +02:00
a40b39e9a2
drtio: structure
2016-10-10 23:12:12 +08:00
Florent Kermarrec
c08caae171
phaser: use qpll
2016-10-10 17:05:42 +02:00
87ec333f55
drtio: implement basic writes, errors, fifo levels on satellite
2016-10-10 00:13:41 +08:00
23b3302200
drtio: implement TSC load in satellite
2016-10-07 19:30:53 +08:00
9b860b26e8
phaser: fix rtio pll inputs
2016-10-07 13:00:42 +02:00
09434ec054
phaser: also adapt rtio_crg
2016-10-07 12:44:22 +02:00
cb0d1549c6
drtio: add rt_packets TX datapath, fixes
2016-10-07 15:35:29 +08:00
Florent Kermarrec
b02a7234f6
phaser: use 125MHz refclk for jesd
2016-10-07 08:59:34 +02:00
whitequark
b52ecda1d5
runtime: make memory map saner.
2016-10-06 18:05:38 +00:00
1193ba4bf4
ad9154: merge csr spaces
2016-10-06 16:21:15 +02:00
4d87f0e9e0
phaser: instantiate jesd204b core, wire up
2016-10-06 14:44:22 +02:00
76bac21d14
drtio: RT RX datapath, untested
2016-10-06 18:51:20 +08:00
4a0eaf0f95
phaser: add jesd204b rtio dds
...
gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
2016-10-05 16:17:50 +02:00
a91ed8394c
rtio: add input-only channel
2016-10-05 16:17:50 +02:00
279f0d568d
rtio: support differential ttl
2016-10-05 16:17:50 +02:00
1e0c6d6d5d
drtio: monitor received link_init
2016-09-30 11:25:06 +08:00
cefb9e1405
drtio: add full link layer
2016-09-27 21:41:57 +08:00
08772f7a71
drtio: add RX ready signaling
2016-09-27 19:02:54 +08:00
95d7cba34a
drtio: fixes, add aux packet test
2016-09-27 12:46:01 +08:00
e59142e344
drtio: use additive scrambler reset by link init
2016-09-27 11:38:05 +08:00
8a92c2c7e5
drtio: add RX link layer, fixes, simple loopback demo
2016-09-27 11:23:29 +08:00
4e47decdbc
drtio: add scrambler/descrambler and test
2016-09-26 14:14:14 +08:00
fa83ad0d9c
drtio: add TX link layer
2016-09-26 12:53:10 +08:00
8280e72e90
gateware: use new misoc CSR mapping API
2016-09-24 20:48:37 +08:00
2bb90a4449
pipistrello: shrink a few more fifos
2016-09-21 02:29:05 +02:00
a7dd356d30
rtio/phy/ttl: support 'set sensitivity and sample' command ( #218 )
2016-09-07 15:42:09 +08:00
051e6e0447
spi: use misoc SPIMachine, closes #314
2016-08-26 14:08:12 +02:00
92f3757c74
spi: give wb-reads a register level
2016-07-31 14:53:19 +02:00
454b48df97
pipistrello: shrink fifos a bit more to relax pnr
2016-07-23 12:55:49 +02:00
7a2405146a
rtio: do not reset DDS and SPI PHYs on RTIO reset ( #503 )
2016-07-09 10:07:19 +08:00
8cb29fcb3b
targets/kc705: redefine user SMAs as 3.3V IO. Closes #502
2016-07-07 14:53:01 +08:00
71921de5bd
spi: do not shift when starting a xfer, closes #495
2016-07-04 12:22:47 +02:00
3bd190e624
gateware/nist_clock: increase DDS bus drive strength. Closes #468
2016-06-07 11:08:19 -04:00
dhslichter
141edb521a
qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
2016-05-19 10:42:03 +08:00
90e678a442
gateware/nist_qc2: increase DDS bus drive strength. Closes #421
2016-05-03 16:29:38 +08:00
9707981c07
targets/kc705: fix default -H option
2016-04-30 00:30:24 +08:00
212ee8ca35
gateware/nist_qc2: substitute FMC
2016-04-14 01:02:34 +08:00
dhslichter
f395a630e0
Updated qc2 pinouts for SPI and 2x DDS bus, update docs
2016-04-13 18:38:34 +08:00
ed1c368e73
gateware: name targets consistently. Closes #290
2016-04-05 16:07:29 +08:00
8f54a1e619
pipistrello: sys_clk 83 -> 75 MHz
...
This should close #341 once migen generates stable output.
2016-03-21 13:47:32 +01:00
900b0cc629
analyzer: make byte_count 64-bit
2016-03-19 19:40:23 +08:00
0e1f75ec49
targets/kc705/qc2: hook up HPC backplane
2016-03-16 16:19:56 +08:00
1bbef94061
analyzer: fix byte_count (again)
2016-03-15 20:49:07 +08:00
85ea70a664
analyzer: fix byte_count
2016-03-15 20:33:08 +08:00
62ac4e3c2e
analyzer: fix EOP generation
2016-03-15 20:25:02 +08:00
b5ec979db3
analyzer: drive wishbone cyc signal
2016-03-15 19:46:12 +08:00
8a6873cab2
analyzer: use EOP, flush pipeline on stop
2016-03-15 17:49:59 +08:00
Florent Kermarrec
8ad799a850
gateware/rtio/analyzer: use new Converter
2016-03-14 15:15:07 +01:00
de718fc819
rtio: fix different address collision detection
2016-03-10 12:15:36 +08:00
f4f95d330b
Merge branch 'master' of github.com:m-labs/artiq
2016-03-10 11:15:30 +08:00
542a375305
rtio: remove NOP suppression capability
...
Back when RTIO was driving TTLs, this functionality made it simpler to use by removing some irrelevant underflows.
The same technique is not applicable to DDS and SPI, so the user will have to deal with such underflows.
This patch makes the behavior of RTIO more consistent and the code simpler.
2016-03-10 09:47:29 +08:00
2e39802a61
rtio/wishbone: make replace configurable
2016-03-10 09:44:05 +08:00
107e5cfbd4
gateware/rtio: factor _BlindTransfer
2016-03-09 19:07:46 +01:00
349a66124b
Merge branch 'master' into rtiobusy
...
* master:
coredevice: fix _DDSGeneric __init__ args
rtio/core: fix syntax
rtio: disable replace on rt2wb channels
examples: dds_bus -> core_dds
fix more multi-DDS-bus problems
runtime: fix dds declarations
support for multiple DDS buses (untested)
2016-03-09 17:58:58 +01:00
3f8e431de6
rtio/core: fix syntax
2016-03-09 17:10:21 +01:00
03b53c3af9
rtio: disable replace on rt2wb channels
2016-03-09 23:37:04 +08:00
446dcfbfbc
Merge commit '9d1903a' into rtiobusy
...
* commit '9d1903a':
coredevice/i2c,ttl,spi: consistent device get
examples/device_db: remove --no-localhost-bind
Monkey-patch asyncio create_server (fixes #253 ).
pipistrello: drop ttls on pmod, add leds back in
pipistrello: try with fewer leds/pmod ttl
2016-03-09 11:55:08 +01:00
f0b0b1bac7
support for multiple DDS buses (untested)
2016-03-09 17:12:50 +08:00
f33baf339f
pipistrello: drop ttls on pmod, add leds back in
2016-03-08 23:34:51 +01:00
f39208c95a
pipistrello: try with fewer leds/pmod ttl
2016-03-08 22:10:47 +01:00
2cb58592ff
rtio: add RTIOBusy
2016-03-08 18:04:34 +01:00
0d431cb019
pipistrello: make pmod extension header, cleanup
2016-03-08 17:07:44 +01:00
a8fe3f50c3
pipistrello: grow fifos a bit (may make ise happier)
2016-03-08 16:17:37 +01:00
00d4775da5
pipistrello: shrink fifos a bit (may make ise happier)
2016-03-08 15:40:12 +01:00
9c11cda7dc
pipistrello: use ttl_simple for pmod[4:8]
2016-03-08 13:52:52 +01:00
104d641c59
pipistrello: move the spi channel like kc705
2016-03-08 13:30:05 +01:00
2180c5af7c
pipistrello: make pmod[4:8] available as ttls
2016-03-08 13:07:58 +01:00
e809e89571
pipistrello: adhere to pmod interface type 2 layout
2016-03-08 13:01:52 +01:00
2953b069dc
rtio: when rtlink addresses are different, issue collision not replace ( fixes #320 )
2016-03-08 15:58:25 +08:00
71105fd0d7
rtio: collision_error -> collision
2016-03-08 15:38:35 +08:00
e8b59b00f6
soc: use add_extra_software_packages, factor builder code
2016-03-07 00:18:47 +08:00
a8a74d7840
targets/kc705: enable I2C for all hardware adapters
2016-03-05 00:19:59 +08:00
7ff0c89d51
kc705.clock: add all spi buses
2016-03-04 00:03:48 +01:00
423ca03f3b
runtime: bit-banged i2c support (untested)
2016-03-03 17:46:42 +08:00
cfe72c72a2
gateware/kc705: add I2C GPIO core for QC2
2016-03-03 15:32:10 +08:00
a901971e58
gateware/soc: factor code to connect CSR device to kernel CPU
2016-03-03 15:12:15 +08:00
b662a6fcbd
gateware/nist_{clock,qc2}: do not conflict with KC705 I2C
2016-03-03 15:10:50 +08:00
9af12230c8
soc: add timer to kernel CPU system
2016-03-03 13:19:17 +08:00
0c97043a20
gateware/nist_clock: pin assignment corrections from David Leibrandt
2016-03-03 10:03:49 +08:00
d3f36ce784
kc705: add false paths for ethernet phy
...
* vivado prefers rsys_clk over sys_clk (despite the assignment hierarchy)
(We need DONT_TOUCH and/or KEEP verilog annotations to fix this)
2016-03-02 19:56:24 +01:00
2cc1dfaee3
kc705: move ttl channels together again, update doc
2016-03-01 19:40:32 +01:00
c2fe9a08ae
gateware.spi: delay only writes to data register, update doc
2016-03-01 14:14:38 +01:00
f2ec8692c0
nist_clock: disable spi1/2
2016-03-01 01:52:46 +01:00
da22ec73df
gateware.spi: rework wb bus sequence
2016-02-29 22:22:08 +01:00
12252abc8f
nist_clock: rename spi*.ce to spi*.cs_n
2016-02-29 22:21:18 +01:00
7ef21f03b9
nist_clock: add SPIMasters to spi buses
2016-02-29 22:19:39 +01:00
7ab7f7d75d
Merge branch 'master' into spimaster
...
* master:
artiq_flash: use term 'gateware'
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
doc: insist that output() must be called on TTLInOut. Closes #297
doc: update install instructions
coredevice: do not give up on UTF-8 errors in log. Closes #300
use m-labs setup for defaults
fix indentation
2016-02-29 20:47:52 +01:00
5fad570f5e
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
2016-03-01 00:35:26 +08:00
dd570720ac
gateware.spi: ack only in cycles
2016-02-29 17:29:37 +01:00
a0083f4501
Revert "gateware/rt2wb: only input when active"
...
This reverts commit 1b08e65fa1
2016-02-29 16:44:11 +01:00
cb8815cc65
Revert "gateware/rt2wb: support combinatorial ack"
...
This reverts commit f73228f248
2016-02-29 16:44:04 +01:00
f73228f248
gateware/rt2wb: support combinatorial ack
2016-02-29 15:40:55 +01:00
1b08e65fa1
gateware/rt2wb: only input when active
2016-02-29 14:56:29 +01:00
572c49f475
use m-labs setup for defaults
2016-02-29 21:35:23 +08:00
eb01b0bfee
gateware.spi: cleanup doc
2016-02-29 12:41:30 +01:00
948fefa69a
gateware.spi: style
2016-02-29 11:48:29 +01:00
ad34927b0a
spi: RTIO_SPI_CHANNEL -> RTIO_FIRST_SPI_CHANNEL
2016-02-29 11:35:49 +01:00
5480099f1b
gateware.spi: rewrite counter bias for timing
2016-02-29 02:28:19 +01:00
9a1d6a51a4
gateware.spi: shorten counters
2016-02-29 01:51:33 +01:00
8d7e92ebae
pipistrello: set RTIO_SPI_CHANNEL
2016-02-29 00:37:00 +01:00
9a881aa430
gateware.spi: simpler clk bias
2016-02-29 00:36:18 +01:00
d5893d15fb
gateware.kc705: make xadc/ams an extension header
2016-02-28 22:41:17 +01:00
312e09150e
kc705/clock: add spi bus for dac on ams101
2016-02-28 21:17:53 +01:00
f8732acece
rtio.spi: drop unused argument
2016-02-28 21:06:20 +01:00
3b6999ac06
gateware.spi: refactor, sim verified
2016-02-28 20:40:06 +01:00
bd9ceb4e12
gateware.spi: add complete spi master logic
2016-02-27 22:47:16 +01:00
ade3eda19a
gateware.pipistrello: use pmod for spi
2016-02-27 11:29:40 +01:00
e7146cc999
gateware.spi: design sketch
2016-02-26 17:03:08 +01:00
fb929c8599
gateware/spi: stubs
2016-02-26 13:11:10 +01:00
a8545fc1f7
targets/kc705: set up user_sma_gpio_n like other TTLs
2016-02-22 22:35:15 +08:00
4946a53456
Revert "targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance"
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This reverts commit 04b0db1a91
2016-02-22 17:52:40 +08:00
68891493a3
analyzer: move common to artiq.protocols
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migen was still pulled in through rtio.__init__.py
2016-01-29 20:26:48 -07:00
d1119d7747
artiq_dir: move out of tools to unlink dependencies
2016-01-25 18:15:50 -07:00
cbb60337ae
refactor Analyzer constants to unlink dependencies
2016-01-25 18:03:48 -07:00
2832d200f2
Merge remote-tracking branch 'm-labs/master' into ppp2
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* m-labs/master:
test/worker: update
gui/log: display level and date information in tooltips
master: add filename in worker log entries. Closes #226
master: finer control of worker exception reporting. Closes #233
conda: add artiq-kc705-nist_clock
gateware: add QC1 docstring
gateware: add clock target from David
gateware: clean up and integrate QC2 modifications from Daniel
add information about CLOCK hardware
2016-01-25 12:17:04 -07:00
8cbb60b370
Merge branch 'master' into ppp2
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* master:
add release notes/process
targets/kc705: fix e664fe3Closes #238
transforms.inferencer: give a suggestion on "raise Exception".
pdq2/mediator: raise instances, not classes
pdq2: wire up more of the pipeline
doc: use actual version
Fix formatting.
doc: add artiq_flash
versioneer: remote tag_prefix = v
2016-01-20 19:29:00 -07:00
18f0ee814d
gateware: add QC1 docstring
2016-01-20 21:27:22 -05:00
db8ba8d6c1
gateware: add clock target from David
2016-01-20 21:23:49 -05:00
b3ba97e431
gateware: clean up and integrate QC2 modifications from Daniel
2016-01-20 21:17:19 -05:00
fa1afb7dd8
add information about CLOCK hardware
2016-01-20 21:06:02 -05:00
cb5fd08713
targets/kc705: fix e664fe3
2016-01-20 09:38:44 -05:00
e664fe38b0
targets/kc705: fix DDS_RTIO_CLK_RATIO for AD9914. Closes #238
2016-01-20 09:18:50 -05:00
57ce78c54d
pipistrello: add rtio.Analyzer()
2016-01-18 19:17:44 -07:00
whitequark
9366a29483
Implement core device storage ( fixes #219 ).
2016-01-10 13:04:55 +00:00
whitequark
577108554f
Move kernel CPU address space up to 0x40800000.
2016-01-07 18:26:11 +00:00
87dd09a71c
gateware: compress bitstreams
2016-01-06 15:40:28 -07:00
04b0db1a91
targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance
2015-12-29 17:00:57 +08:00
ba6c527819
gateware/targets: add RTIO log channels
2015-12-26 22:44:01 +08:00
080752092c
gateware/rtio: add LogChannel
2015-12-26 22:43:28 +08:00
9ba8dfbf23
gateware/rtio/core: avoid potential python bug
2015-12-26 22:11:57 +08:00
8691f69a3c
gateware/rtio/analyzer: suppress spurious initial reset messages
2015-12-21 18:32:08 +08:00
