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678 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 58b7bdcecc sayma_amc: refactor RTM FPGA code 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 96fc4a21e8 sayma_amc: remove dummy FPGA pin assignment testing code 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 6aa68e1715 sayma_rtm2: select filtered clock from Si5324 2019-10-04 22:56:16 +08:00
Sebastien Bourdeauducq 6cb0f5de59 sayma_amc: enable DRTIO switching 2019-10-04 22:55:23 +08:00
Sebastien Bourdeauducq 0cf8a46bbd sayma_amc2: select filtered clock from Si5324 2019-10-04 21:28:26 +08:00
Sebastien Bourdeauducq 991c686d72 kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template 2019-09-11 15:51:53 +08:00
Sebastien Bourdeauducq 7492a59f6d kasli_generic: add SUServo support (#1343) 2019-09-11 11:12:48 +08:00
Sebastien Bourdeauducq 21021beb08 kasli: remove opticlock (moved to kasli_generic) 2019-09-09 15:03:10 +08:00
Sebastien Bourdeauducq cfb5ef5548 kasli_generic: add Novogorny support 2019-09-09 14:54:34 +08:00
Sebastien Bourdeauducq 1fb317778a eem/grabber: allow third EEM to be specified 2019-08-29 18:58:12 +08:00
Sebastien Bourdeauducq 43e58c939c sayma: drop MasterDAC 
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.

Now Sayma works fine with Kasli as a master, which is simpler.
 2019-06-14 14:06:16 +08:00
Sebastien Bourdeauducq b04e15741b drop SI5324_SAYMA_REF 2019-06-14 14:03:48 +08:00
Sebastien Bourdeauducq bc2cfd77f5 metlino: add EEMs 2019-05-19 18:16:00 +08:00
Sebastien Bourdeauducq cdef50c0dd sayma_amc: Urukul v1.3 2019-05-19 16:54:38 +08:00
Sebastien Bourdeauducq 9dcaae6395 metlino: use variant output directory 2019-05-19 16:24:51 +08:00
Sebastien Bourdeauducq b4779969d0 metlino: work around vivado bug (#1230) 2019-05-19 11:27:27 +08:00
Sebastien Bourdeauducq 874542f33f add Metlino support 2019-05-19 10:57:43 +08:00
Sebastien Bourdeauducq fda3cb2482 kasli_generic: add edge counter support 2019-05-09 17:19:11 +08:00
Robert Jördens ead9a42842 kasli: remove VLBAIMaster, VLBAISatellite variants 2019-05-08 15:58:25 +00:00
Robert Jördens 0c9b810501 kasli: remove PTB/PTB2/LUH/HUB variants 
see sinara-systems and nix-scripts repos
 2019-05-08 15:51:18 +00:00
Robert Jördens 1d2cc60e0d kasli_generic: support ext_ref 2019-05-08 15:51:18 +00:00
David Nadlinger 4d215cf541 firmware: Add Si5324 config for 125 MHz ext ref 
PLL divider settings as suggested by DSPLLsim 5.1.
 2019-04-15 22:22:19 +01:00
Sebastien Bourdeauducq 97b7ed557b sayma_amc: do not use SFP0 (now used for Ethernet) 2019-04-12 18:47:18 +08:00
Chris Ballance 4499ef1748 kasli: only add moninj core if there are probes to monitor 2019-03-24 14:09:52 +08:00
Sebastien Bourdeauducq 5d31cf2268 sayma_rtm2: si5324_clkout -> cdr_clk_clean 2019-03-23 13:48:36 +08:00
Sebastien Bourdeauducq 560849e693 sayma_amc: add DRTIO transceiver on rtm_amc_link for v2 hardware 2019-03-23 13:41:22 +08:00
Sebastien Bourdeauducq bbb8c00518 sayma_amc: default to satellite variant 2019-03-23 13:37:55 +08:00
Sebastien Bourdeauducq 18fbe0b081 sayma_rtm_drtio: support v2 hardware 2019-03-23 13:31:28 +08:00
Sebastien Bourdeauducq c7205ad82f sayma_rtm: preliminary v2 support 2019-03-23 12:37:03 +08:00
Sebastien Bourdeauducq 33b28f6e56 sayma_amc: add placeholder code to use DDMTD signals on v2 hardware 2019-03-21 17:37:22 +08:00
Sebastien Bourdeauducq 2ec5a58c59 sayma_amc: si5324_clkout -> cdr_clk_clean 2019-03-21 14:09:33 +08:00
Sebastien Bourdeauducq e47ba4b35e kasli_generic: fix identifier string 2019-03-08 19:57:20 +08:00
Sebastien Bourdeauducq 62c7f75a9e sayma_amc: support hardware revisions 2019-02-25 23:49:45 +08:00
Sebastien Bourdeauducq d45249197c siphaser: improve ultrascale clock routing 2019-02-25 23:00:01 +08:00
Sebastien Bourdeauducq de3992bbdd kasli: remove HUST variants (supported by kasli_generic) 2019-02-23 15:44:17 +08:00
Sebastien Bourdeauducq 791f830ef6 kasli_generic: support DRTIO 2019-02-23 15:41:05 +08:00
Sebastien Bourdeauducq 1c35c051a5 kasli: remove variants supported by generic builder 2019-02-22 23:08:49 +08:00
Sebastien Bourdeauducq 8edc2318ab style 2019-02-22 17:19:20 +08:00
Sebastien Bourdeauducq 6ad2e13515 kasli: add generic builder (WIP) 2019-02-12 19:18:09 +08:00
Sebastien Bourdeauducq ff4e4f15ed kasli: expose base SoC classes 2019-02-12 18:33:27 +08:00
Sebastien Bourdeauducq 1cfd26dc2e kasli: add UNSW variant 2019-02-08 17:51:51 +08:00
Sebastien Bourdeauducq b56c7cec1e kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target 
Urukul sync is not reliable at 125/1000
 2019-02-05 11:24:45 +08:00
Sebastien Bourdeauducq ea431b6982 sayma_rtm: use 150MHz RTIO freq for DDMTD 2019-01-31 20:43:44 +08:00
Sebastien Bourdeauducq ec230d6560 sayma: move SYSREF DDMTD to the RTM 
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
 2019-01-31 20:39:33 +08:00
Sebastien Bourdeauducq 8119000982 sayma_rtm_drtio: use Si5324 soft reset 
Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.

Allows using Si5324 + HMC7043 chips at the same time.

Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
 2019-01-31 19:43:54 +08:00
Sebastien Bourdeauducq 9ae57fd51e sayma: pass rtio_clk_freq to DDMTD core 2019-01-29 15:06:45 +08:00
Sebastien Bourdeauducq 47312e55d3 sayma: set RTIO_FREQUENCY in MasterDAC 2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq 443d6d8688 sayma_amc: pass RTIO clock frequency to SiPhaser 2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq 9966e789fc sayma: simplify Ultrascale LVDS T false path 
Recommended by Xilinx.
 2019-01-25 23:40:48 +08:00
Sebastien Bourdeauducq 359fb1f207 sayma: fix DDMTD STA 2019-01-25 23:39:19 +08:00
Sebastien Bourdeauducq cb04230f86 sayma: SYSREF setup/hold validation demonstration 
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
 2019-01-25 16:58:58 +08:00
Sebastien Bourdeauducq 3356717316 sayma: DDMTD SYSREF measurement demonstration 2019-01-25 16:00:31 +08:00
Sebastien Bourdeauducq 4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation) 
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
 2019-01-25 13:47:04 +08:00
Sebastien Bourdeauducq 07b5b0d36d kasli: adapt Master target to new hardware 2019-01-24 18:27:15 +08:00
Sebastien Bourdeauducq 154269b77a kasli: fix HUST satellite Urukul 2019-01-23 17:59:43 +08:00
Sebastien Bourdeauducq d7e6f104d2 kasli: add HUST variants 2019-01-23 14:11:51 +08:00
Sebastien Bourdeauducq 81f2b2c864 kasli: remove unpopulated Tester EEMs 
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
 2019-01-23 12:14:44 +08:00
Sebastien Bourdeauducq 9ee5fea88d kasli: support optional SATA port for DRTIO 2019-01-22 18:06:48 +08:00
Sebastien Bourdeauducq bff8c8cb05 kasli: add Berkeley variant 2019-01-21 17:44:17 +08:00
Sebastien Bourdeauducq a2ff2cc173 sayma_amc: use more selective IOBUFDS false path 2019-01-19 11:47:50 +08:00
David Nadlinger 1c71ae636a examples: Add edge counters to kasli_tester variant 
This enables test_edge_counter on the CI system.
 2019-01-15 10:55:07 +00:00
Sebastien Bourdeauducq 4cb9f77fd8 sayma_amc: fix Master timing constraints 2019-01-13 13:53:07 +08:00
Sebastien Bourdeauducq 9b213b17af sayma_amc: forward RTM UART in Master variant as well 2019-01-09 18:57:57 +08:00
Sebastien Bourdeauducq c7b18952b8 sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad 2019-01-09 13:47:08 +08:00
Sebastien Bourdeauducq 3217488824 add Sayma RTM DRTIO target 2019-01-07 00:13:47 +08:00
Sebastien Bourdeauducq 66b3132c28 sayma_amc: fix RTIO TSC instantiation 2019-01-06 14:54:32 +08:00
Sebastien Bourdeauducq 2100a8b1f1 sayma_amc: more fighting with vivado timing analyzer 2019-01-05 12:25:30 +08:00
Sebastien Bourdeauducq 62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
Sebastien Bourdeauducq 175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
Sebastien Bourdeauducq 77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq cc58318500 siphaser: autocalibrate skew using RX synchronizer 
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
 2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
Sebastien Bourdeauducq 53e79f553f Merge branch 'master' into new 2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq 78d4b3a7da gateware/targets: expose variant lists 
This allows writing scripts that build all variants.
 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq c990b5e4f1 Merge remote-tracking branch 'origin/master' into new 2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq ad0254c17b Merge branch 'switching125' into new 2018-11-07 22:03:18 +08:00
Sebastien Bourdeauducq efd735a6ab Revert "drtio: monitor RTIOClockMultiplier PLL (#1155)" 
This reverts commit 469a66db61.
 2018-11-07 22:01:03 +08:00
Robert Jördens ba4bf6e59b kasli: don't pass rtio pll feedback through bufg 
UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:58:55 +00:00
Robert Jördens b6e4961b0f kasli: lower RTIO clock jitter 
* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:43:19 +00:00
Robert Jördens e17e458c58 ptb2: add sync to urukul0 for ad9910 usage 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 10:06:51 +00:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync' 
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
 2018-11-05 19:54:30 +01:00
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:16 +01:00
Robert Jördens d8a5951a13 kasli: add sync to LUH, HUB, Opticlock 
for #1143, also add missing LUH device db

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:14 +01:00
Robert Jördens 4269d5ad5c tester: add urukul sync 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:52 +01:00
Robert Jördens 60d3bc63a7 ptb: back out urukul-sync 
... for backwards compatibility.

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:50 +01:00
Robert Jördens 0433e8f4fe urukul: add sync_in generator 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:30 +01:00
Sebastien Bourdeauducq bc4a8157c0 kasli: add tsinghua2 2018-11-01 18:26:37 +08:00
Sebastien Bourdeauducq 6357a50d33 kasli: update nudt variant 2018-10-15 18:04:57 +08:00
Sebastien Bourdeauducq 469a66db61 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-10-08 14:50:02 +02:00
Sebastien Bourdeauducq 86fe6b0594 kasli: add NUDT variant 2018-10-04 23:20:09 +08:00
Sebastien Bourdeauducq a89bd6b684 kasli: swap Urukul EEMs for Tester 
Updated to Urukul 1.3.
 2018-10-04 23:19:31 +08:00
Sebastien Bourdeauducq 9f96b6bcda kasli: use 125MHz DRTIO freq for testing 2018-10-04 10:41:01 +08:00
Sebastien Bourdeauducq 969a305c5a Merge branch 'master' into switching125 2018-10-04 10:08:42 +08:00
Robert Jördens d0ee2c2955 opticlock: external 100 MHz 2018-09-28 19:05:18 +02:00
Sebastien Bourdeauducq 3b3fddb5a4 kasli: add mitll2 2018-09-27 23:21:52 +08:00
Sebastien Bourdeauducq b92350b0f6 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-09-26 10:52:08 +08:00
Sebastien Bourdeauducq 212892d92f style 2018-09-26 10:13:33 +08:00
Sebastien Bourdeauducq 73f0de7c79 sayma: DRTIO master fixes 2018-09-20 11:15:45 +08:00
Sebastien Bourdeauducq cd61ee858c kasli: fix satellite TSC instantiation 2018-09-15 14:06:54 +08:00
Sebastien Bourdeauducq 420e1cb1d0 cri: fix firmware routing table access 2018-09-12 18:08:16 +08:00
Sebastien Bourdeauducq 7ec45efdcf kasli: add missing cri_con to Satellite 2018-09-10 20:16:09 +08:00
Sebastien Bourdeauducq 7ae44f3417 firmware: add routing table (WIP) 2018-09-09 21:49:28 +08:00
Sebastien Bourdeauducq 496d1b08fd kasli: enable routing in Master 2018-09-09 21:48:12 +08:00
Sebastien Bourdeauducq ec302747e0 kasli: add DRTIO repeaters 2018-09-09 16:27:39 +08:00
Sebastien Bourdeauducq 87e0384e97 drtio: separate aux controller 
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
 2018-09-05 17:56:58 +08:00
Sebastien Bourdeauducq 1450e17a73 sayma: adapt to TSC and DRTIOSatellite changes 2018-09-05 12:10:41 +08:00
Sebastien Bourdeauducq 19ae9ac1b1 kc705: adapt to TSC changes 2018-09-05 12:07:28 +08:00
Sebastien Bourdeauducq 3d531cc923 kasli: adapt to TSC and DRTIOSatellite changes 2018-09-05 12:06:47 +08:00
Robert Jördens 47eb37e212 VLBAI{Master,Slave}: align rtio channels with PTB 2018-09-04 10:39:45 +00:00
Robert Jördens e7dba34475 kasli/tester: fill all 12 EEM 2018-08-29 18:09:09 +00:00
Robert Jördens fbf05db5ab kasli: add VLBAI Master and Satellite 2018-08-29 17:53:48 +00:00
Robert Jördens 9584c30a1f kasli: DRTIO Base: flexible rtio_clk_freq 2018-08-29 17:53:48 +00:00
Sebastien Bourdeauducq 9b6ea47b7a kasli: use SFP LEDs to show DRTIO link status. Closes #1073 2018-08-19 13:04:41 +08:00
Sebastien Bourdeauducq 167e97efd2 sayma: support external RTM clocking 2018-08-17 22:57:54 +08:00
Sebastien Bourdeauducq 49f7a1610f sayma: use GTP_CLK1 only for all variants (#1080) 2018-08-07 20:53:14 +08:00
Sebastien Bourdeauducq 9ce6233926 kasli: fix SYSU TTL directions 2018-08-07 19:29:28 +08:00
Sebastien Bourdeauducq 65f198bdee kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example 2018-08-06 16:53:13 +08:00
Sebastien Bourdeauducq b023865b42 sayma: instantiate dummy IBUFDS_GTE3 on unused but driven Si5324 clock pins 
Solve same problem as e83ee3a0 but channels cannot be independently disabled.
 2018-08-05 23:02:41 +08:00
Sebastien Bourdeauducq e83ee3a07a hmc7043: disable GTP_CLK1 when not in use 
Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
 2018-08-03 10:03:52 +08:00
Sebastien Bourdeauducq 3638a966e1 kasli: add false path between RTIO and CL clocks 2018-07-21 13:26:13 +08:00
Sebastien Bourdeauducq 25170a53e5 sayma: add back Urukul and Zotino 2018-07-18 10:27:54 +08:00
Sebastien Bourdeauducq 4fdc20bb11 sayma: disable Urukul and Zotino for now 
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
 2018-07-17 20:08:21 +08:00
Sebastien Bourdeauducq d724bd980c sayma: add EEMs to Master 2018-07-17 18:58:23 +08:00
Sebastien Bourdeauducq 3645a6424e sayma: fix Master build 2018-07-17 18:56:33 +08:00
Sebastien Bourdeauducq 3168b193e6 kc705: remove Zotino and Urukul 
* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
 2018-07-17 17:48:57 +08:00
Sebastien Bourdeauducq b2695d03ed sayma: remove with_sawg from Master variant 2018-07-15 17:38:29 +08:00
Sebastien Bourdeauducq b27fa8964b add variant in identifier string 
Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059
 2018-07-15 17:21:17 +08:00
Sebastien Bourdeauducq 88fb9ce4d6 sayma_rtm: add hmc7043_gpo monitoring 2018-07-11 19:04:29 +08:00
Sebastien Bourdeauducq 29e5c95afa sayma_rtm: minor cleanup 2018-07-11 19:02:59 +08:00
Sebastien Bourdeauducq 7f05e0c121 sayma_rtm: remove UART loopback 
RTM power supply issues are fixed now, plus this will get in the way of satman support.
 2018-07-11 19:00:18 +08:00
Sebastien Bourdeauducq 509562ddbf kasli: add WIPM target 2018-07-06 15:41:28 +08:00
Sebastien Bourdeauducq 729ce58f98 sayma: use GTP_CLK1 to clock DRTIO satellite transceiver 
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
 2018-06-28 11:23:40 +08:00
Sebastien Bourdeauducq a65721d649 sayma: put RTM clock tree into the siphaser loop 
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
 2018-06-27 21:46:55 +08:00
Sebastien Bourdeauducq c750de2955 sayma: add many-port pure DRTIO master 2018-06-25 18:21:22 +08:00
Sebastien Bourdeauducq 68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets 
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
 2018-06-23 10:44:38 +08:00
Sebastien Bourdeauducq 60b22217ce sayma: set DRTIO master HMC830_REF to 100MHz 2018-06-22 10:10:09 +08:00
Sebastien Bourdeauducq e6d1726754 sayma: add RTIO log to DRTIO master 2018-06-22 00:05:22 +08:00
Sebastien Bourdeauducq 83428961ad sayma: add SAWG and JESD to DRTIO master 2018-06-22 00:04:22 +08:00
Sebastien Bourdeauducq 8b3c12e6eb sayma: clock DRTIO master transceiver from HMC7043 2018-06-21 22:34:44 +08:00
Sebastien Bourdeauducq b28ff587c5 sayma: add sysref sampler to DRTIO master 2018-06-21 22:28:34 +08:00
Sebastien Bourdeauducq 28fb0fd754 sayma: add SYSREF sampler gateware 2018-06-20 17:48:35 +08:00
Sebastien Bourdeauducq 75b6cea52f sayma: add SAWG to DRTIO satellite 2018-06-19 19:12:10 +08:00
Sebastien Bourdeauducq 433273dd95 sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite 2018-06-19 14:33:48 +08:00
Sebastien Bourdeauducq 6403a0d5d1 sayma_amc: update without-sawg description 2018-06-19 13:52:05 +08:00
Sebastien Bourdeauducq d29b3dd588 hmc830: compile-time configurable reference frequency 2018-06-19 13:47:32 +08:00
Sebastien Bourdeauducq 6f3ed81626 targets/sayma_rtm: fix description 2018-06-18 17:46:53 +08:00
Robert Jördens 32484a62de sayma_amc: remove unused imports 2018-06-17 13:09:44 +02:00
Robert Jördens 53ab255c00 sayma_amc: enable slave fpga loading (#813) 2018-06-16 12:47:26 +02:00
Robert Jördens 1029ac870b sayma_rtm: don't drive txen pins 
pins disabled by config
necessary for using that pin as DIN (#813)
 2018-06-13 16:11:30 +00:00