5437f0e3e3
rtio: make sequence errors consistently asychronous
2017-09-29 14:40:06 +08:00
d7ef07a0c2
rtio/sed: document architecture
2017-09-26 16:44:23 +08:00
9905b8723b
rtio/sed: support negative latency compensation
2017-09-26 16:11:08 +08:00
4112e403de
rtio/sed: latency compensation
2017-09-26 15:09:07 +08:00
aa8fc81a87
rtio: allow specifying glbl_fine_ts_width externally
2017-09-23 22:34:55 +08:00
5cf0693758
rtio: use BlindTransfer to report collision and busy errors to sys domain
2017-09-21 22:31:56 +08:00
d74a7d272e
rtio: fix/cleanup parameters
2017-09-21 15:59:48 +08:00
07d3f87c51
rtio/sed: min_space → buffer_space
2017-09-21 14:36:13 +08:00
d8aa75b742
rtio/sed: add minimum buffer space reporting
2017-09-20 11:27:57 +08:00
ddcd6065e8
rtio: drive InputCollector.coarse_timestamp
2017-09-19 17:46:38 +08:00
ff8e17ab89
rtio: use input collector module
2017-09-19 15:53:35 +08:00
4dc80e3d05
rtio: add missing import
2017-09-19 15:53:23 +08:00
d37577a8a1
rtio: add input collector module
2017-09-19 15:30:30 +08:00
6dc9cad2c9
rtio: add explanation about cri.counter
2017-09-19 12:05:12 +08:00
81d6317053
rtio/sed: take global fine TS width
2017-09-18 11:30:49 +08:00
65baca8c57
rtio: clean up error-prone rtlink.get_or_zero()
2017-09-17 16:11:36 +08:00
e2c1d4f3d5
rtio/sed: trigger collision error on non-data replace
2017-09-16 17:01:23 +08:00
0e25154e25
rtio/sed: quash writes to LogChannel
2017-09-16 15:19:30 +08:00
1cfe90b1d9
rtio/sed/Gates: fix fine_ts_width computation
2017-09-16 15:09:21 +08:00
a3bb6c167c
rtio: use SED
2017-09-16 14:13:42 +08:00
131f5e4a3b
rtio/sed/LaneDistributor: fix CRI address
2017-09-16 14:13:01 +08:00
a155a481b1
rtio/sed: add top-level core
2017-09-16 14:04:56 +08:00
92c63ce2e4
rtio/sed: rename fifos/gates, refactor tsc
2017-09-16 14:03:48 +08:00
ac52c7c818
rtio/sed/LaneDistributor: style
2017-09-16 14:02:37 +08:00
6b7a1893c7
rtio/sed/OutputDriver: support channels with different fine timestamp widths
2017-09-16 10:53:30 +08:00
f39ee7ad62
rtio/sed: fix seqn_width
2017-09-16 10:52:37 +08:00
064503f224
rtio/sed/LaneDistributor: support specifying existing CRI
2017-09-16 10:52:13 +08:00
1cb05f3ed5
rtio/sed/LaneDistributor: persist underflow/sequence error until next write
2017-09-16 10:51:44 +08:00
3c922463a0
style
2017-09-15 15:36:46 +08:00
8e5ab90129
rtio/sed: add FIFO wrapper
2017-09-15 15:36:34 +08:00
490c9815a2
rtio/sed: add TSC/gate (untested)
2017-09-14 19:53:21 +08:00
181cb42ba8
rtio/sed: centralize all layouts in one file
2017-09-14 19:52:31 +08:00
1b61442bc3
rtio/sed: fix lane spreading and enable by default
2017-09-13 22:48:10 +08:00
8cfe2ec53a
rtio/sed: fix sequence number width computation
2017-09-13 22:11:41 +08:00
a92a955d1e
rtio/sed: use __all__
2017-09-13 18:17:22 +08:00
c74abccfd5
rtio/sed: lane distributor fixes
2017-09-13 17:50:06 +08:00
bdd96084c5
rtio/sed: add lane distributor (untested)
2017-09-13 00:07:26 +08:00
00ff3f5b0d
rtio/sed: fix output driver busy output
2017-09-11 23:04:52 +08:00
666bc600a2
rtio/sed: add output driver (untested)
2017-09-11 11:10:28 +08:00
1d2ebbe60f
rtio/sed: make ON payload layout configurable, add latency function
2017-09-11 09:06:40 +08:00
c5d6a2ba1a
rtio/sed: more output network fixes
2017-09-10 23:41:04 +08:00
96505a1cd9
rtio/sed: output network fixes
2017-09-10 23:23:10 +08:00
5646e19dc3
rtio/sed: add output network (untested)
2017-09-10 14:38:43 +08:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
...
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
...
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
c0100ebc56
rtio: fix indentation
2017-04-06 12:08:13 +08:00
207453efcd
rtio: add a missing case for collision reporting
2017-04-06 11:28:16 +08:00
whitequark
47632f81b1
gateware: CRIArbiter -> CRISwitch.
2017-04-05 16:10:39 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
12249dac57
rtio: do not clear asynchronous error flags on RTIO reset
2017-04-03 00:20:30 +08:00
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
b74d6fb9ba
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
whitequark
4de336fbe9
gateware: reverse bytes of SDRAM word, not bits.
2017-03-17 11:16:46 +00:00
whitequark
6b63322106
gateware: reverse SDRAM words in RTIO DMA engine.
2017-03-17 07:29:28 +00:00
whitequark
4b14887ddb
gateware: work around ISE/Vivado bugs with very wide shifts.
2017-03-17 07:29:28 +00:00
a7de58b604
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
497c795d8c
drtio: input support (untested)
2017-03-13 23:54:44 +08:00
1e6a33b586
rtio: handle input timeout in gateware
...
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
2017-03-03 17:37:47 +08:00
d2f2415b50
analyzer: use CRI and connect at RTIO core
...
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
7d6ebabc1b
reorganize core device communication code
2017-02-27 18:37:30 +08:00
c66efc0279
moninj: do not require a rsys clock domain
2017-02-20 15:52:48 +08:00
86f6b391b7
ad9xxx -> ad9_dds
2017-01-04 11:34:52 +01:00
6b998581cc
rtio: use same reset for counter_rtio whatever the interface delay is
2016-12-15 09:28:13 +08:00
8381db279f
sawg: wire up all HBF outputs, latency compensation in phys, simplify
2016-12-14 19:16:07 +01:00
6cdb96c5e0
rtio: add support for latency compensation in phy
...
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
2016-12-14 19:16:07 +01:00
c63fa46430
Merge branch 'phaser2'
...
* phaser2: (157 commits)
sawg/hbf: tweak pipeline for timing
fir: register multiplier output
conda/phaser: build-depend on numpy
sawg: reduce coefficient width
sawg: fix latency
test/fir: needs mpl. don't run by default
test/sawg: patch spline
sawg: use ParallelHBFCascade to AA [WIP]
fir: add ParallelHBFCascade
fir: add ParallelFIR and test
gateware/dsp: add FIR and test
README_PHASER: update
sawg: documentation
sawg: extract spline
sawg: document
sawg: demo_2tone
sawg: round to int64
gateware/phaser -> gateware/ad9154_fmc_ebz
phaser: fix typo
sawg: merge set/set64
...
2016-12-12 17:31:39 +01:00
7196bc21c1
rtio: simplify error reset logic
...
Channel is always selected when reset is issued.
2016-12-12 17:35:10 +08:00
bc36bda94a
perform RTIO init on comms CPU side
2016-12-09 14:16:55 +08:00
f3c50a37ca
rtio: always read full DMA sequence
2016-12-06 01:05:47 +08:00
c413d95b49
rtio: fix DMA get_csrs
2016-12-05 18:12:09 +08:00
b677c69faf
rtio: fix handling of o_status in DMA
2016-12-05 18:01:48 +08:00
75ea13748a
rtio: fix DMA data MSB and stop signaling, self-checking unittest
2016-12-05 18:01:48 +08:00
a5834765d0
rtio: more DMA fixes, better stopping mechanism
2016-12-05 18:01:48 +08:00
30bce5ad35
rtio: DMA fixes
2016-12-05 18:01:48 +08:00
88ad054ab6
Merge branch 'drtio'
2016-12-03 23:25:17 +08:00
3931d8097b
rtio: fix DMA TimeOffset stream.connect
2016-12-01 16:43:46 +08:00
7c59688a12
rtio: simple DMA fixes
2016-12-01 16:30:48 +08:00
46dbc44c8f
rtio: export DMA and CRIInterconnectShared
2016-12-01 16:30:29 +08:00
6c97a97d8c
rtio: support single-master CRI arbiter
2016-12-01 16:30:11 +08:00
a318243083
rtio: CRI arbiter (untested)
2016-12-01 15:41:43 +08:00
cd3f68ba76
rtio: DMA core (untested)
2016-11-30 18:43:19 +08:00
85f2467e2c
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
2016-11-28 15:01:46 +08:00
5460202220
drtio: typo
2016-11-28 14:35:21 +08:00
4e1b497742
drtio: typo
2016-11-28 14:34:58 +08:00
c419c422fa
drtio: support for local RTIO core
2016-11-28 14:33:26 +08:00
1c84d1ee59
Merge branch 'master' into phaser2
...
* master:
rtio: support differential ttl
RELEASE_NOTES: int(a, width=b) removal, use int32/64
pc_rpc: use ProactorEventLoop on Windows (#627 )
2016-11-24 15:05:49 +01:00
95c885b580
rtio: support differential ttl
2016-11-24 15:04:12 +01:00
2d62a89143
rtio: use large data register
2016-11-23 23:23:27 +08:00
9941f3557d
rtio: use only CRI commands for rio/rio_phy resets
2016-11-23 23:19:14 +08:00
347609d765
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-23 15:03:36 +01:00
