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artiq/artiq/gateware/rtio
2016-12-09 14:16:55 +08:00
..
phy rtio: support differential ttl 2016-11-24 15:04:12 +01:00
__init__.py rtio: export DMA and CRIInterconnectShared 2016-12-01 16:30:29 +08:00
analyzer.py perform RTIO init on comms CPU side 2016-12-09 14:16:55 +08:00
cdc.py adapt to migen/misoc changes 2016-10-31 00:53:01 +08:00
core.py perform RTIO init on comms CPU side 2016-12-09 14:16:55 +08:00
cri.py perform RTIO init on comms CPU side 2016-12-09 14:16:55 +08:00
dma.py rtio: always read full DMA sequence 2016-12-06 01:05:47 +08:00
moninj.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
rtlink.py rtio: remove NOP suppression capability 2016-03-10 09:47:29 +08:00