Commit Graph

5419 Commits

Author SHA1 Message Date
ed6aa29897 jesd204sync: print more information on test_slip_ddmtd error 2019-01-29 16:47:29 +08:00
2e8decbce3 kasli_sawgmaster: generate a HMC830 clock with Urukul 2019-01-29 15:06:45 +08:00
9ae57fd51e sayma: pass rtio_clk_freq to DDMTD core 2019-01-29 15:06:45 +08:00
90c9fa446f test: add array transfer test
200 kB/s, more than a factor of 10 slower than the bare string transfer

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-28 14:30:44 +00:00
7a5d28b73d jesd204sync: test SYSREF period 2019-01-28 19:11:38 +08:00
1a42e23fb4 jesd204sync: print DDMTD SYSREF final alignment delta 2019-01-28 18:39:16 +08:00
eebff6d77f jesd204sync: fix max_phase_deviation 2019-01-28 18:38:18 +08:00
b9e3fab49c jesd204sync: improve messaging 2019-01-28 18:37:46 +08:00
145f08f3fe jesd204sync: update SYSREF S/H limit deviation tolerance
Follows the increased DDMTD resolution.
2019-01-28 18:21:31 +08:00
ba21dc8498 jesd204sync: improve messaging 2019-01-28 18:08:20 +08:00
3acee87df2 firmware: improve DDMTD resolution using dithering/averaging 2019-01-28 16:04:04 +08:00
cfe66549ff jesd204sync: cleanup DDMTD averaging code 2019-01-28 14:14:50 +08:00
2b0d63db23 hmc830_7043: support 125MHz RTIO 2019-01-28 13:44:08 +08:00
bdd4e52a53 ad9154: support 125MHz RTIO 2019-01-28 13:43:52 +08:00
47312e55d3 sayma: set RTIO_FREQUENCY in MasterDAC 2019-01-28 13:43:28 +08:00
443d6d8688 sayma_amc: pass RTIO clock frequency to SiPhaser 2019-01-28 09:49:03 +08:00
3b6f47886e firmware: print more info on DDMTD stability error 2019-01-27 23:06:11 +08:00
74fdd04622 firmware: test DDMTD stability 2019-01-27 20:39:12 +08:00
81b0046f98 ddmtd: add deglitchers 2019-01-27 20:38:41 +08:00
8254560577 sayma: properly determine SYSREF coarse calibration target 2019-01-27 16:00:36 +08:00
214394e3b0 sayma: reimplement DAC SYSREF autocalibration 2019-01-27 15:28:39 +08:00
fdbf1cc2b2 sayma: rework DAC SYSREF margin validation
Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
7e5c062c2c firmware: bypass channel divider for HMC7043 DCLK 2019-01-27 11:49:34 +08:00
f73ffe44f9 firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.

Needs cleanup and optimization/characterization.
2019-01-27 09:51:24 +08:00
8632b553d2 ddmtd: use IOB register to sample input 2019-01-27 09:50:02 +08:00
d1ef036948 kasli_sawgmaster: initialize SAWG phase according to RTIO TSC 2019-01-27 09:49:31 +08:00
9966e789fc sayma: simplify Ultrascale LVDS T false path
Recommended by Xilinx.
2019-01-25 23:40:48 +08:00
359fb1f207 sayma: fix DDMTD STA 2019-01-25 23:39:19 +08:00
cb04230f86 sayma: SYSREF setup/hold validation demonstration
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
3356717316 sayma: DDMTD SYSREF measurement demonstration 2019-01-25 16:00:31 +08:00
4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation)
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
cc9420d2c8 hmc7043: fix divider programming 2019-01-25 11:48:50 +08:00
8c5a502591 ad53xx: ignore F3 (reserved)
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-24 15:50:46 +01:00
bbac92442f sayma: check hmc7043 slip period 2019-01-24 20:13:43 +08:00
a92cc91dcb kasli_sawgmaster: correctly tune DDS and SAWG 2019-01-24 19:37:14 +08:00
f8b39b0b9a sayma: enable 2X DAC interpolation
Seems to work just fine and gets one clock divider out of the way.
2019-01-24 18:28:01 +08:00
07b5b0d36d kasli: adapt Master target to new hardware 2019-01-24 18:27:15 +08:00
154269b77a kasli: fix HUST satellite Urukul 2019-01-23 17:59:43 +08:00
3b5fd3ac11 kasli_tester: fix grabber test 2019-01-23 17:59:25 +08:00
330c5610e9 ad9912: fix imports 2019-01-23 17:59:08 +08:00
390f05f762 firmware: use smoltcp release 2019-01-23 16:15:05 +08:00
d7e6f104d2 kasli: add HUST variants 2019-01-23 14:11:51 +08:00
81f2b2c864 kasli: remove unpopulated Tester EEMs
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
2019-01-23 12:14:44 +08:00
b692981c8e ad9910: add note about red front panel led
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 12:49:42 +01:00
a0eba5b09b satman: support Grabber 2019-01-22 19:36:13 +08:00
2e3555de85 firmware: fix compilation error with more than 1 Grabber 2019-01-22 19:35:46 +08:00
9ee5fea88d kasli: support optional SATA port for DRTIO 2019-01-22 18:06:48 +08:00
91e375ce6a ad9910: don't reset the input divide-by-two
suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221;

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 09:37:20 +00:00
81ff3d4b29 ad9912: add some slack after init 2019-01-21 17:10:58 +00:00
a9678dd9f2 test_frontends: always skip GUI programs
The "import PyQt5" hack breaks on nix/hydra.
2019-01-21 23:41:07 +08:00
84f7d006e8 ad9910: add precision about tune_io_update_delay/tune_sync_delay order 2019-01-21 19:40:55 +08:00
30051133b7 urukul: fix typos 2019-01-21 19:40:55 +08:00
30b2f54baa kasli_tester: skip Zotino test when no Zotino is present 2019-01-21 18:11:41 +08:00
bff8c8cb05 kasli: add Berkeley variant 2019-01-21 17:44:17 +08:00
a987d2b2e5 kasli_tester: skip Grabber test when no Grabber is present 2019-01-21 17:43:48 +08:00
David Nadlinger
4ba4e9c540 test_scheduler: Test for hang when exiting with running experiments
The respective code path in artiq.master.scheduler._mk_worker_method
wasn't previously covered.
2019-01-20 19:45:50 +00:00
David Nadlinger
0dab7ecd73 master: Include RID in worker exception messages
This helps when debugging unexpected shutdown problems
after the fact.
2019-01-20 19:45:50 +00:00
David Nadlinger
e24e893303 master/scheduler: Fix misleading indentation [nfc] 2019-01-20 19:45:47 +00:00
David Nadlinger
e165a9a352 sync_struct: Factor action strings out into enum and document them [nfc] 2019-01-19 20:19:17 +00:00
David Nadlinger
c213ab13ba sync_struct: Notifier.{read -> raw_view}, factor out common dict update code [nfc] 2019-01-19 20:19:17 +00:00
David Nadlinger
bd71852427 sync_struct: Tweak variable name to avoid confusion with init mod action [nfc] 2019-01-19 20:19:17 +00:00
David Nadlinger
90c144a685 test_pc_rpc: Remove leftover debug print [nfc]
This tidies up the test suite output, and we have verbose asserts
to show further information on breakage, should it occur.
2019-01-19 20:18:33 +00:00
a2ff2cc173 sayma_amc: use more selective IOBUFDS false path 2019-01-19 11:47:50 +08:00
40187d1957 ad9910: support configurable refclk divider and pll bypass
for #1248

* also always keep refclk input divider (by two) reset
2019-01-18 12:23:53 +00:00
385916a9a4 ad9912: support configurable clk_div 2019-01-18 12:16:08 +00:00
2bea5e3d58 urukul: support configurable refclk divider
for #1248
2019-01-18 12:09:32 +00:00
689714965b monkey_patches: disable for Python >= 3.6.7
3.6 >=7 are fixed
3.7.0 is incompatible with the monkey patches and they do more harm than good
3.7 >=1 are fixed
2019-01-15 20:29:20 +08:00
David Nadlinger
1c71ae636a examples: Add edge counters to kasli_tester variant
This enables test_edge_counter on the CI system.
2019-01-15 10:55:07 +00:00
David Nadlinger
67a6882e91 examples: Fix kasli_tester device_db offset comments 2019-01-15 10:55:07 +00:00
David Nadlinger
a565f77538 Add gateware input event counter 2019-01-15 10:55:07 +00:00
4cb9f77fd8 sayma_amc: fix Master timing constraints 2019-01-13 13:53:07 +08:00
David Nadlinger
6c52359e59 coredevice: Add _mu suffix to AD991x ref_time arguments
GitHub: Fixes #1243.
2019-01-12 17:34:35 +00:00
David Nadlinger
24b1b9a480 Add smoke test for frontend commands
This ensures that at least --help works for all the commands,
preventing regressions like that in f3323a35d5.
2019-01-12 13:50:53 +00:00
whitequark
425cd7851e compiler: first monomorphize ints, then casts.
Fixes #1242.
2019-01-12 13:40:12 +00:00
whitequark
49682d0159 Improve Python 3.7 compatibility.
async is now a full (non-contextual) keyword.

There are two more instances:
   - artiq/frontend/artiq_client.py
   - artiq/devices/thorlabs_tcube/driver.py

It is not immediately clear how to fix those, so they are left for
later work.
2019-01-12 13:17:59 +00:00
David Nadlinger
f3323a35d5 artiq_influxdb: Unbreak after verbosity_args rename
This fixes commit f2c1d32e54.
2019-01-12 12:02:22 +00:00
David Nadlinger
48fc175a6b coredevice.ttl: More imperative mood in docstrings [nfc]
This follows Python conventions (PEP257) and unifies the style with
other comments.
2019-01-12 12:01:55 +00:00
Drew
f2c1d32e54 frontend: add --version flag to cmd line args (#1181) 2019-01-12 09:47:47 +08:00
David Nadlinger
3e84ec2bf1 coredevice.ad9910: Fix phase tracking ref_time passing
This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).

This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
2019-01-12 00:47:38 +00:00
Drew
66861e6708 test_pc_rpc: fix equality bug (#1188) (#1239)
Fixes bug from 5108ed8. Truth value of multi-element numpy array is
not defined. Completes #1186 and fixes/amends #1188.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-11 10:15:44 +08:00
101671fbbf core_analyzer: support uniform VCD time intervals
close #1236

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-10 19:35:09 +01:00
Drew
99a0f61b35 artiq_client: remove custom input validation for built-in argparse (#1185) 2019-01-10 12:58:11 +08:00
Drew
721c6f3bcc pc_rpc: fix handling of type annotations 2019-01-10 12:13:22 +08:00
088530604e test_ad9910: relax tests
* tune_sync_delay: the opposite IO_UPDATE to SYNC_CLK alignment may not be perfectly
mis-aligned
* set_mu_speed: seems to be slower on the buildbot

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 17:27:42 +00:00
19748fe495 ad9910: fix RTIO fine timestamp nudging
Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.

close #1229

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 17:22:57 +00:00
b25ab1fc88 ad9910: add more slack in tune_sync_delay
close #1235

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 16:07:31 +00:00
9b213b17af sayma_amc: forward RTM UART in Master variant as well 2019-01-09 18:57:57 +08:00
c7b18952b8 sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad 2019-01-09 13:47:08 +08:00
62599c5f91 firmware: use consistent terminology 2019-01-09 13:46:18 +08:00
Drew
b3b0b6f0a5 artiq_influxdb: clarify argparse groups (#1212)
Make names of argparse group variables relate to what they're doing.
Meets Flake8.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-09 11:40:55 +08:00
David Nadlinger
101ed5d534 examples: Fix DRTIO destination indices (#1231)
Using the default routing table, links numbers and destinations
are offset by 1, as destination 0 is local RTIO.
2019-01-09 11:40:15 +08:00
Drew
40370c4d45 Docs: fix build warnings (#1234)
* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP

Found while building docs. Forgot to refactor strings.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>

* spi2: reformat update_xfer_duration_mu docstring

update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-09 11:39:23 +08:00
David Nadlinger
4fb434674d coredevice: Fix ad9910 __all__ exports 2019-01-08 18:55:26 +00:00
887cb110a7 firmware: fix default DRTIO routing table 2019-01-08 20:46:53 +08:00
David Nadlinger
cadde970e1 urukul: Expand CPLD sync_sel explanation [nfc] 2019-01-08 02:37:58 +00:00
David Nadlinger
7bcdeb825b ad9910: Add inverse FTW/ASF conversions 2019-01-08 02:18:14 +00:00
David Nadlinger
4d793d7149 ad9910: Truncate phase word to 16 bits
This avoids overflowing into the asf portion of the register.
2019-01-08 02:18:14 +00:00
332bd6090f satman: wait for CPLL/QPLL lock after setting drtio_transceiver::stable_clkin 2019-01-07 17:09:19 +08:00
3217488824 add Sayma RTM DRTIO target 2019-01-07 00:13:47 +08:00
b5501aaf00 firmware: program I2C switch on Sayma RTM 2019-01-06 14:54:52 +08:00
66b3132c28 sayma_amc: fix RTIO TSC instantiation 2019-01-06 14:54:32 +08:00
6e43c41103 firmware: support building without SDRAM 2019-01-05 23:41:30 +08:00
cf9447ab77 rtio/cri: remove unneeded CSR management 2019-01-05 23:40:45 +08:00
2c3510497b firmware: fix not(has_spiflash) build 2019-01-05 23:40:03 +08:00
2100a8b1f1 sayma_amc: more fighting with vivado timing analyzer 2019-01-05 12:25:30 +08:00
Drew Risinger
b58d59a9e7 pyon: fix grammar in module docstring.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-04 19:31:08 +00:00
a93fdb8c9d drtio: disable all destinations in gateware at startup
Otherwise, kernels fail to get a RTIODestinationUnreachable exception when attempting
to reach a DRTIO destination that has never been up.
2019-01-04 23:42:12 +08:00
62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
0972d61e81 ttl_serdes_ultrascale: use GTH clock domains 2019-01-03 20:50:04 +08:00
f007895fad drtio/gth_ultrascale: fix rtiox clock domain 2019-01-03 20:49:38 +08:00
10ebf63c47 jesd204_tools: get the Vivado timing analyzer to behave 2019-01-03 20:22:35 +08:00
d6a3172a3e update copyright year 2019-01-03 20:21:34 +08:00
4af8fd6a0d ttl_serdes_ultrascale: fix Input 2019-01-03 20:14:54 +08:00
175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
cc58318500 siphaser: autocalibrate skew using RX synchronizer
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
Drew
d60b95f481 tdr.py: typo (#1220) 2018-12-18 18:47:09 +00:00
a7d4d3bda9 ad9910: CONT_RECIRCULATE -> CONT_RAMPUP 2018-12-17 13:25:00 +00:00
35bdf26f01 Merge branch 'ad9910-ram' 2018-12-17 21:16:44 +08:00
David Nadlinger
e608d6ffd3 coredevice, firmware: Add rtio_input_timestamped_data
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
2018-12-15 00:35:04 +00:00
David Nadlinger
8e30c4574b firmware: Treat timestamps consistently as signed [nfc]
This matches other functions and the ARTIQ Python side, but
isn't actually an ABI change.
2018-12-15 00:02:18 +00:00
38ce7ab8ff sync_struct: handle TimeoutError as subscriber disconnection. Closes #1215 2018-12-13 06:58:54 +08:00
79eadb9465 ad9910: add RAM mode methods
* also refactor the CFR1 access into a method

c.f. #1154

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 14:54:16 +00:00
6df4ae934f eem: name the servo submodule
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos

close #1201

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
efd400b02c ad9910: style [nfc]
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:25 +01:00
David Nadlinger
d4c393b2a8 firmware/ksupport: Update cfg(not(has_rtio)) stub signatures
This fixes up 8caea0e6d3,
but it is unclear whether anyone even uses a `not(has_rtio)`
configuration at this point.
2018-12-11 01:22:48 +00:00
d90eb3ae88 ad9910: add read64()
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:27:00 +00:00
baf88050fd urukul: expand attenuator HITL unittests
* read back with cleared backing state
* individual channel settings
* check backing state

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:06:12 +00:00
Kaifeng
cc143d5fec kasli_tester: add support for windows platform. (#1204) 2018-12-05 14:06:45 +01:00
6aa341bc44 test_loopback_gate_timing: fix lat_offset 2018-12-02 20:52:32 +08:00
421834fa3e compiler: document Target.little_endian 2018-12-02 19:07:18 +08:00
981a77834a compiler: use default triple to determine data_layout for JIT 2018-12-02 18:52:13 +08:00
d931967e5c fix previous commits 2018-12-02 18:32:03 +08:00
dd03fdfd1a typo 2018-12-02 18:26:54 +08:00
8940009e1a compiler: pass data_layout string to llvm.create_target_data before determining endianness 2018-12-02 18:26:19 +08:00
2e66788c6c compiler: support little endian target when storing now 2018-12-02 17:40:34 +08:00
7e14f3ca4e compiler,gateware: atomic now stores 2018-12-02 05:06:46 +08:00
fd00021a52 ctlmgr: do not raise exceptions in Controllers.__setitem__. Closes #1198 2018-12-01 18:09:58 +08:00
7f55376c75 test_loopback_gate_timing: print input timing for debugging 2018-12-01 18:09:53 +08:00
dce4f036db grabber: work around windows numpy int peculiarity (same as a81c12de9) 2018-11-30 18:41:14 +08:00
156afb48ee language: fix syscall arg handling 2018-11-30 17:59:24 +08:00
Paweł K
57caa7b149 artiq_flash: add command to erase flash memory (#1197) 2018-11-28 12:33:32 +02:00
c56c0ba41f rtio/dds: use write-only RT2WB
This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
2018-11-26 07:38:15 +08:00
09141e5bee rtio/wishbone: support write-only interface 2018-11-26 07:38:06 +08:00
450a035f9e suservo: move overflowing RTIO address bits into data 2018-11-26 06:54:20 +08:00
ae8ef18f47 rtlink: sanity-check parameters 2018-11-26 01:14:02 +08:00
b32e89444c Merge branch 'master' into new 2018-11-26 01:02:19 +08:00
af9ea1f324 gui: update background 2018-11-26 01:01:36 +08:00