forked from M-Labs/artiq
typo
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@ -151,7 +151,7 @@ class LLVMIRGenerator:
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])
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assert self.lldatalayout in "eE"
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self.little_endian = self.self.lldatalayout[0] == "e"
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self.little_endian = self.lldatalayout[0] == "e"
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def needs_sret(self, lltyp, may_be_large=True):
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if isinstance(lltyp, ll.VoidType):
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