forked from M-Labs/artiq
ad9910: support configurable refclk divider and pll bypass
for #1248 * also always keep refclk input divider (by two) reset
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@ -75,8 +75,10 @@ class AD9910:
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:param sw_device: Name of the RF switch device. The RF switch is a
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TTLOut channel available as the :attr:`sw` attribute of this instance.
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:param pll_n: DDS PLL multiplier. The DDS sample clock is
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f_ref/4*pll_n where f_ref is the reference frequency (set in the parent
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f_ref/clk_div*pll_n where f_ref is the reference frequency and
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clk_div is the reference clock divider (both set in the parent
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Urukul CPLD instance).
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:param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
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:param pll_cp: DDS PLL charge pump setting.
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:param pll_vco: DDS PLL VCO range selection.
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:param sync_delay_seed: SYNC_IN delay tuning starting value.
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@ -88,12 +90,11 @@ class AD9910:
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set this to the delay tap number returned.
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus",
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"ftw_per_hz", "pll_n", "io_update_delay",
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"sysclk_per_mu"}
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"ftw_per_hz", "io_update_delay", "sysclk_per_mu"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
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io_update_delay=0):
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io_update_delay=0, pll_en=1):
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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@ -102,24 +103,30 @@ class AD9910:
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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assert 12 <= pll_n <= 127
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clk = self.cpld.refclk/[4, 1, 2, 4][self.cpld.clk_div]
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self.pll_en = pll_en
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self.pll_n = pll_n
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assert self.cpld.refclk/4 <= 60e6
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sysclk = self.cpld.refclk*pll_n/4 # Urukul clock fanout divider
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self.pll_vco = pll_vco
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self.pll_cp = pll_cp
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if pll_en:
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sysclk = clk*pll_n
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assert clk <= 60e6
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assert 12 <= pll_n <= 127
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assert 0 <= pll_vco <= 5
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vco_min, vco_max = [(370, 510), (420, 590), (500, 700),
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(600, 880), (700, 950), (820, 1150)][pll_vco]
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assert vco_min <= sysclk/1e6 <= vco_max
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assert 0 <= pll_cp <= 7
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else:
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sysclk = clk
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assert sysclk <= 1e9
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self.ftw_per_hz = (1 << 32)/sysclk
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self.sysclk_per_mu = int(round(sysclk*self.core.ref_period))
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assert self.sysclk_per_mu == sysclk*self.core.ref_period
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assert 0 <= pll_vco <= 5
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vco_min, vco_max = [(370, 510), (420, 590), (500, 700),
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(600, 880), (700, 950), (820, 1150)][pll_vco]
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assert vco_min <= sysclk/1e6 <= vco_max
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self.pll_vco = pll_vco
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assert 0 <= pll_cp <= 7
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self.pll_cp = pll_cp
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if sync_delay_seed >= 0 and not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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self.sync_delay_seed = sync_delay_seed
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if self.sync_delay_seed >= 0:
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assert self.sysclk_per_mu == sysclk*self.core.ref_period
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self.io_update_delay = io_update_delay
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self.phase_mode = PHASE_MODE_CONTINUOUS
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@ -340,24 +347,27 @@ class AD9910:
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# sync timing validation disable (enabled later)
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self.write32(_AD9910_REG_CFR2, 0x01010020)
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self.cpld.io_update.pulse(1*us)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_n << 1))
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cfr3 = (0x08078000 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_en << 8) |
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(self.pll_n << 1))
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self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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self.cpld.io_update.pulse(1*us)
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self.write32(_AD9910_REG_CFR3, cfr3)
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self.cpld.io_update.pulse(1*us)
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if blind:
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delay(100*ms)
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else:
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# Wait for PLL lock, up to 100 ms
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for i in range(100):
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sta = self.cpld.sta_read()
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lock = urukul_sta_pll_lock(sta)
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delay(1*ms)
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if lock & (1 << self.chip_select - 4):
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break
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if i >= 100 - 1:
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raise ValueError("PLL lock timeout")
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if self.pll_en:
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self.write32(_AD9910_REG_CFR3, cfr3)
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self.cpld.io_update.pulse(1*us)
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if blind:
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delay(100*ms)
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else:
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# Wait for PLL lock, up to 100 ms
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for i in range(100):
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sta = self.cpld.sta_read()
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lock = urukul_sta_pll_lock(sta)
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delay(1*ms)
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if lock & (1 << self.chip_select - 4):
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break
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if i >= 100 - 1:
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raise ValueError("PLL lock timeout")
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delay(10*us) # slack
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if self.sync_delay_seed >= 0:
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self.tune_sync_delay(self.sync_delay_seed)
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delay(1*ms)
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