forked from M-Labs/artiq
jesd204sync: test SYSREF period
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@ -232,6 +232,27 @@ pub fn sysref_rtio_align() -> Result<(), &'static str> {
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}
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}
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pub fn test_sysref_period() -> Result<(), &'static str> {
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info!("testing SYSREF period...");
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let half_sysref_period = hmc7043::SYSREF_DIV/hmc7043::FPGA_CLK_DIV/2;
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for _ in 0..32 {
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for _ in 0..half_sysref_period {
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if !sysref_get_sample()? {
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return Err("unexpected SYSREF value during period test");
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}
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sysref_slip_rtio_cycle();
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}
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for _ in 0..half_sysref_period {
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if sysref_get_sample()? {
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return Err("unexpected SYSREF value during period test");
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}
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sysref_slip_rtio_cycle();
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}
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}
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info!(" ...done");
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Ok(())
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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test_ddmtd_stability(true, 4)?;
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test_ddmtd_stability(false, 1)?;
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@ -279,6 +300,7 @@ pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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info!(" ...done, delta={}", delta);
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sysref_rtio_align()?;
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test_sysref_period()?;
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Ok(())
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}
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