forked from M-Labs/artiq
ad9910: fix RTIO fine timestamp nudging
Previously the TSC was truncated to an even coarse RTIO periods before doing the setting SPI xfer. Afterwards the the IO update pulse would introduce at least one but less than two RTIO cycles. Ultimately the RTIO TSC was truncated again to even. If the SPI xfer takes an odd number of RTIO periods, then a subsequent xfer would collide. close #1229 Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -400,8 +400,9 @@ class AD9910:
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"""
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if phase_mode == _PHASE_MODE_DEFAULT:
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phase_mode = self.phase_mode
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# Align to coarse RTIO which aligns SYNC_CLK
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at_mu(now_mu() & ~0xf)
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# Align to coarse RTIO which aligns SYNC_CLK. I.e. clear fine TSC
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# This will not cause a collision or sequence error.
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at_mu(now_mu() & ~7)
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if phase_mode != PHASE_MODE_CONTINUOUS:
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# Auto-clear phase accumulator on IO_UPDATE.
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# This is active already for the next IO_UPDATE
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@ -418,8 +419,8 @@ class AD9910:
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self.write64(_AD9910_REG_PROFILE0 + profile,
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(asf << 16) | (pow_ & 0xffff), ftw)
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delay_mu(int64(self.io_update_delay))
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYSCLK
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at_mu(now_mu() & ~0xf)
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYN_CCLK
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at_mu(now_mu() & ~7) # clear fine TSC again
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if phase_mode != PHASE_MODE_CONTINUOUS:
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self.set_cfr1()
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# future IO_UPDATE will activate
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@ -673,16 +674,17 @@ class AD9910:
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self.write32(_AD9910_REG_RAMP_RATE, 0x00010000)
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# dFTW = 1, (work around negative slope)
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self.write64(_AD9910_REG_RAMP_STEP, -1, 0)
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# delay io_update after RTIO/2 edge
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t = now_mu() + 0x10 & ~0xf
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# delay io_update after RTIO edge
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t = now_mu() + 8 & ~7
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at_mu(t + delay_start)
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self.cpld.io_update.pulse_mu(32 - delay_start) # realign
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# assumes a maximum t_SYNC_CLK period
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self.cpld.io_update.pulse_mu(16 - delay_start) # realign
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# disable DRG autoclear and LRR on io_update
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self.set_cfr1()
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# stop DRG
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self.write64(_AD9910_REG_RAMP_STEP, 0, 0)
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at_mu(t + 0x1000 + delay_stop)
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self.cpld.io_update.pulse_mu(32 - delay_stop) # realign
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self.cpld.io_update.pulse_mu(16 - delay_stop) # realign
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ftw = self.read32(_AD9910_REG_FTW) # read out effective FTW
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delay(100*us) # slack
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# disable DRG
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