forked from M-Labs/artiq
Merge branch 'ad9910-ram'
This commit is contained in:
commit
35bdf26f01
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@ -13,7 +13,10 @@ urukul_sta_smp_err = urukul.urukul_sta_smp_err
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__all__ = [
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"AD9910",
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"PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE", "PHASE_MODE_TRACKING"
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"PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE", "PHASE_MODE_TRACKING",
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"RAM_DEST_FTW", "RAM_DEST_POW", "RAM_DEST_ASF", "RAM_DEST_POWASF",
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"RAM_MODE_DIRECTSWITCH", "RAM_MODE_RAMPUP", "RAM_MODE_BIDIR_RAMP",
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"RAM_MODE_CONT_BIDIR_RAMP", "RAM_MODE_CONT_RECIRCULATE",
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]
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@ -44,6 +47,19 @@ _AD9910_REG_PROFILE6 = 0x14
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_AD9910_REG_PROFILE7 = 0x15
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_AD9910_REG_RAM = 0x16
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# RAM destination
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RAM_DEST_FTW = 0
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RAM_DEST_POW = 1
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RAM_DEST_ASF = 2
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RAM_DEST_POWASF = 3
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# RAM MODES
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RAM_MODE_DIRECTSWITCH = 0
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RAM_MODE_RAMPUP = 1
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RAM_MODE_BIDIR_RAMP = 2
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RAM_MODE_CONT_BIDIR_RAMP = 3
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RAM_MODE_CONT_RECIRCULATE = 4
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class AD9910:
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"""
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@ -222,6 +238,82 @@ class AD9910:
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data_low)
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@kernel
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def write_ram(self, data):
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"""Write data to RAM.
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The profile to write to and the step, start, and end address
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need to be configured before and separately using
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:meth:`set_profile_ram` and the parent CPLD `set_profile`.
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:param data List(int32): Data to be written to RAM.
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
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self.chip_select)
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self.bus.write(_AD9910_REG_RAM << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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for i in range(len(data) - 1):
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self.bus.write(data[i])
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data[len(data) - 1])
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@kernel
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def read_ram(self, data):
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"""Read data from RAM.
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The profile to read from and the step, start, and end address
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need to be configured before and separately using
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:meth:`set_profile_ram` and the parent CPLD `set_profile`.
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:param data List(int32): List to be filled with data read from RAM.
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
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self.chip_select)
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self.bus.write((_AD9910_REG_RAM | 0x80) << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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preload = 8
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for i in range(len(data) - 1):
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self.bus.write(0)
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if i >= preload:
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data[i - preload] = self.bus.read()
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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for i in range(preload + 1):
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data[(len(data) - preload - 1) + i] = self.bus.read()
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@kernel
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def set_cfr1(self, power_down=0b0000, phase_autoclear=0,
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drg_load_lrr=0, drg_autoclear=0,
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internal_profile=0, ram_destination=0, ram_enable=0):
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"""Set CFR1. See the AD9910 datasheet for parameter meanings.
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This method does not pulse IO_UPDATE.
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:param power_down: Power down bits.
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:param phase_autoclear: Autoclear phase accumulator.
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:param drg_load_lrr: Load digital ramp generator LRR.
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:param drg_autoclear: Autoclear digital ramp generator.
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:param internal_profile: Internal profile control.
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:param ram_destination: RAM destination
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(:const:`_AD9910_RAM_DEST_FTW`, :const:`_AD9910_RAM_DEST_POW`,
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:const:`_AD9910_RAM_DEST_ASF`, :const:`_AD9910_RAM_DEST_POWASF`).
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:param ram_enable: RAM mode enable.
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"""
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self.write32(_AD9910_REG_CFR1,
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(ram_enable << 31) |
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(ram_destination << 29) |
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(internal_profile << 17) |
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(drg_load_lrr << 15) |
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(drg_autoclear << 14) |
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(phase_autoclear << 13) |
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(power_down << 4) |
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2) # SDIO input only, MSB first
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@kernel
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def init(self, blind=False):
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"""Initialize and configure the DDS.
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@ -233,7 +325,7 @@ class AD9910:
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:param blind: Do not read back DDS identity and do not wait for lock.
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"""
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# Set SPI mode
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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self.set_cfr1()
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self.cpld.io_update.pulse(1*us)
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delay(1*ms)
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if not blind:
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@ -274,13 +366,13 @@ class AD9910:
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def power_down(self, bits=0b1111):
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"""Power down DDS.
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:param bits: power down bits, see datasheet
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:param bits: Power down bits, see datasheet
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"""
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self.write32(_AD9910_REG_CFR1, 0x00000002 | (bits << 4))
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self.set_cfr1(power_down=bits)
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self.cpld.io_update.pulse(1*us)
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@kernel
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def set_mu(self, ftw, pow=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT,
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def set_mu(self, ftw, pow_=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT,
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ref_time=-1, profile=0):
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"""Set profile 0 data in machine units.
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@ -295,7 +387,7 @@ class AD9910:
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phase modes.
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:param ftw: Frequency tuning word: 32 bit.
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:param pow: Phase tuning word: 16 bit unsigned.
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:param pow_: Phase tuning word: 16 bit unsigned.
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:param asf: Amplitude scale factor: 14 bit unsigned.
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:param phase_mode: If specified, overrides the default phase mode set
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by :meth:`set_phase_mode` for this call.
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@ -313,7 +405,7 @@ class AD9910:
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if phase_mode != PHASE_MODE_CONTINUOUS:
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# Auto-clear phase accumulator on IO_UPDATE.
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# This is active already for the next IO_UPDATE
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self.write32(_AD9910_REG_CFR1, 0x00002002)
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self.set_cfr1(phase_autoclear=1)
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if phase_mode == PHASE_MODE_TRACKING and ref_time < 0:
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# set default fiducial time stamp
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ref_time = 0
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@ -322,15 +414,51 @@ class AD9910:
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# Also no need to use IO_UPDATE time as this
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# is equivalent to an output pipeline latency.
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dt = int32(now_mu()) - int32(ref_time)
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pow += dt*ftw*self.sysclk_per_mu >> 16
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self.write64(_AD9910_REG_PROFILE0 + profile, (asf << 16) | pow, ftw)
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pow_ += dt*ftw*self.sysclk_per_mu >> 16
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self.write64(_AD9910_REG_PROFILE0 + profile, (asf << 16) | pow_, ftw)
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delay_mu(int64(self.io_update_delay))
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYSCLK
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at_mu(now_mu() & ~0xf)
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if phase_mode != PHASE_MODE_CONTINUOUS:
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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self.set_cfr1()
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# future IO_UPDATE will activate
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return pow
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return pow_
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@kernel
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def set_profile_ram(self, start, end, step=1, profile=0, nodwell_high=0,
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zero_crossing=0, mode=1):
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"""Set the RAM profile settings.
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:param start: Profile start address in RAM.
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:param end: Profile end address in RAM (last address).
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:param step: Profile address step size (default: 1).
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:param profile: Profile index (0 to 7) (default: 0).
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:param nodwell_high: No-dwell high bit (default: 0,
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see AD9910 documentation).
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:param zero_crossing: Zero crossing bit (default: 0,
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see AD9910 documentation).
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:param mode: Profile RAM mode (:const:`RAM_MODE_DIRECTSWITCH`,
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:const:`RAM_MODE_RAMPUP`, :const:`RAM_MODE_BIDIR_RAMP`,
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:const:`RAM_MODE_CONT_BIDIR_RAMP`, or
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:const:`RAM_MODE_CONT_RECIRCULATE`, default:
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:const:`RAM_MODE_RAMPUP`)
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"""
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hi = (step << 8) | (end >> 2)
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lo = ((end << 30) | (start << 14) | (nodwell_high << 5) |
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(zero_crossing << 3) | mode)
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self.write64(_AD9910_REG_PROFILE0 + profile, hi, lo)
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@kernel
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def set_ftw(self, ftw):
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self.write32(_AD9910_REG_FTW, ftw)
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@kernel
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def set_asf(self, asf):
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self.write32(_AD9910_REG_ASF, asf)
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@kernel
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def set_pow(self, pow_):
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self.write32(_AD9910_REG_POW, pow_)
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency):
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@ -351,10 +479,22 @@ class AD9910:
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return int32(round(amplitude*0x3ffe))
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@portable(flags={"fast-math"})
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def pow_to_turns(self, pow):
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def pow_to_turns(self, pow_):
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"""Return the phase in turns corresponding to a given phase offset
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word."""
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return pow/0x10000
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return pow_/0x10000
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@kernel
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def set_frequency(self, frequency):
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return self.set_ftw(self.frequency_to_ftw(frequency))
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@kernel
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def set_amplitude(self, amplitude):
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return self.set_asf(self.amplitude_to_asf(amplitude))
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@kernel
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def set_phase(self, turns):
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return self.set_pow(self.turns_to_pow(turns))
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@kernel
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def set(self, frequency, phase=0.0, amplitude=1.0,
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@ -363,9 +503,9 @@ class AD9910:
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.. seealso:: :meth:`set_mu`
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:param ftw: Frequency in Hz
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:param pow: Phase tuning word in turns
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:param asf: Amplitude in units of full scale
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:param frequency: Frequency in Hz
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:param phase: Phase tuning word in turns
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:param amplitude: Amplitude in units of full scale
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:param phase_mode: Phase mode constant
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:param ref_time: Fiducial time stamp in machine units
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:param profile: Profile to affect
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@ -509,8 +649,7 @@ class AD9910:
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:return: Odd/even SYNC_CLK cycle indicator.
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"""
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# set up DRG
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# DRG ACC autoclear and LRR on io update
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self.write32(_AD9910_REG_CFR1, 0x0000c002)
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self.set_cfr1(drg_load_lrr=1, drg_autoclear=1)
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# DRG -> FTW, DRG enable
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self.write32(_AD9910_REG_CFR2, 0x01090000)
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# no limits
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@ -524,7 +663,7 @@ class AD9910:
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at_mu(t + delay_start)
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self.cpld.io_update.pulse_mu(32 - delay_start) # realign
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# disable DRG autoclear and LRR on io_update
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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self.set_cfr1()
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# stop DRG
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self.write64(_AD9910_REG_RAMP_STEP, 0, 0)
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at_mu(t + 0x1000 + delay_stop)
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