forked from M-Labs/artiq
ad9910: Truncate phase word to 16 bits
This avoids overflowing into the asf portion of the register.
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@ -415,7 +415,8 @@ class AD9910:
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# is equivalent to an output pipeline latency.
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dt = int32(now_mu()) - int32(ref_time)
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pow_ += dt*ftw*self.sysclk_per_mu >> 16
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self.write64(_AD9910_REG_PROFILE0 + profile, (asf << 16) | pow_, ftw)
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self.write64(_AD9910_REG_PROFILE0 + profile,
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(asf << 16) | (pow_ & 0xffff), ftw)
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delay_mu(int64(self.io_update_delay))
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYSCLK
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at_mu(now_mu() & ~0xf)
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