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urukul: Expand CPLD sync_sel explanation [nfc]

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David Nadlinger 2019-01-08 02:37:58 +00:00
parent 7bcdeb825b
commit cadde970e1
1 changed files with 4 additions and 2 deletions
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6
artiq/coredevice/urukul.py
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@ -133,8 +133,10 @@ class CPLD:
internal MMCX. For hardware revision <= v1.2 valid options are: 0 -
either XO or MMCX dependent on component population; 1 SMA. Unsupported
clocking options are silently ignored.
:param sync_sel: SYNC_IN selection. 0 corresponds to SYNC_IN over EEM
from FPGA. 1 corresponds to SYNC_IN from DDS0.
:param sync_sel: SYNC (multi-chip synchronisation) signal source selection.
0 corresponds to SYNC_IN being supplied by the FPGA via the EEM
connector. 1 corresponds to SYNC_OUT from DDS0 being distributed to the
other chips.
:param rf_sw: Initial CPLD RF switch register setting (default: 0x0).
Knowledge of this state is not transferred between experiments.
:param att: Initial attenuator setting shift register (default: