forked from M-Labs/artiq
firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO. Needs cleanup and optimization/characterization.
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8632b553d2
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f73ffe44f9
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@ -3,6 +3,67 @@ use board_misoc::{csr, clock, config};
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use hmc830_7043::hmc7043;
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use ad9154;
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fn average_2phases(a: i32, b:i32, modulo: i32) -> i32 {
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let diff = ((a - b + modulo/2 + modulo) % modulo) - modulo/2;
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return (modulo + b + diff/2) % modulo;
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}
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fn average_phases(phases: &[i32], modulo: i32) -> i32 {
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if phases.len() == 1 {
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panic!("input array length must be a power of 2");
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} else if phases.len() == 2 {
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average_2phases(phases[0], phases[1], modulo)
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} else {
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let cut = phases.len()/2;
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average_2phases(
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average_phases(&phases[..cut], modulo),
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average_phases(&phases[cut..], modulo),
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modulo)
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}
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}
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const DDMTD_N_SHIFT: i32 = 6;
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const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT;
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const SYSREF_SH_PRECISION_SHIFT: i32 = 5;
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const SYSREF_SH_PRECISION: i32 = 1 << SYSREF_SH_PRECISION_SHIFT;
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const SYSREF_SH_MOD: i32 = 1 << (DDMTD_N_SHIFT + SYSREF_SH_PRECISION_SHIFT);
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fn measure_ddmdt_phase_raw() -> i32 {
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unsafe { csr::sysref_ddmtd::dt_read() as i32 }
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}
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fn measure_ddmdt_phase() -> i32 {
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let mut measurements = [0; SYSREF_SH_PRECISION as usize];
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for i in 0..SYSREF_SH_PRECISION {
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measurements[i as usize] = measure_ddmdt_phase_raw() << SYSREF_SH_PRECISION_SHIFT;
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clock::spin_us(10);
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}
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average_phases(&measurements, SYSREF_SH_MOD) >> SYSREF_SH_PRECISION_SHIFT
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}
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fn test_slip_ddmtd() -> Result<(), &'static str> {
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// expected_step = (RTIO clock frequency)*(DDMTD N)/(HMC7043 CLKIN frequency)
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let expected_step = 4;
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let tolerance = 1;
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info!("testing HMC7043 SYSREF slip against DDMTD...");
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let mut old_phase = measure_ddmdt_phase();
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for _ in 0..1024 {
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hmc7043::sysref_slip();
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let phase = measure_ddmdt_phase();
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let step = (DDMTD_N + old_phase - phase) % DDMTD_N;
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if (step - expected_step).abs() > tolerance {
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error!(" ...got unexpected step: {}", step);
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return Err("HMC7043 SYSREF slip produced unexpected DDMTD step");
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}
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old_phase = phase;
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}
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info!(" ...passed");
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Ok(())
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}
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fn sysref_sh_error() -> bool {
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unsafe {
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csr::sysref_sampler::sh_error_reset_write(1);
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@ -13,13 +74,150 @@ fn sysref_sh_error() -> bool {
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}
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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for _ in 0..256 {
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#[derive(Default)]
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struct SysrefShLimits {
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rising_phases: [i32; SYSREF_SH_PRECISION as usize],
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falling_phases: [i32; SYSREF_SH_PRECISION as usize],
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}
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fn measure_sysref_sh_limits() -> Result<SysrefShLimits, &'static str> {
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let mut ret = SysrefShLimits::default();
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let mut nslips = 0;
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let mut rising_n = 0;
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let mut falling_n = 0;
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let mut previous = sysref_sh_error();
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while rising_n < SYSREF_SH_PRECISION || falling_n < SYSREF_SH_PRECISION {
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hmc7043::sysref_slip();
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let dt = unsafe { csr::sysref_ddmtd::dt_read() };
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let sh_error = sysref_sh_error();
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info!("dt={} sysref_sh_error={}", dt, sh_error);
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nslips += 1;
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if nslips > 1024 {
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return Err("too many slips and not enough SYSREF S/H error transitions");
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}
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let current = sysref_sh_error();
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let phase = measure_ddmdt_phase();
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if current && !previous && rising_n < SYSREF_SH_PRECISION {
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ret.rising_phases[rising_n as usize] = phase << SYSREF_SH_PRECISION_SHIFT;
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rising_n += 1;
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}
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if !current && previous && falling_n < SYSREF_SH_PRECISION {
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ret.falling_phases[falling_n as usize] = phase << SYSREF_SH_PRECISION_SHIFT;
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falling_n += 1;
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}
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previous = current;
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}
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Ok(ret)
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}
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fn max_phase_deviation(average: i32, phases: &[i32]) -> i32 {
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let mut ret = 0;
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for phase in phases.iter() {
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let deviation = (phase - average).abs();
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if deviation > ret {
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ret = deviation;
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}
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}
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return ret;
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}
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fn reach_sysref_ddmtd_target(target: i32, tolerance: i32) -> Result<(), &'static str> {
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let mut phase = measure_ddmdt_phase();
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let mut nslips = 0;
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while (phase - target).abs() > tolerance {
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hmc7043::sysref_slip();
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nslips += 1;
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if nslips > 1024 {
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return Err("failed to reach SYSREF DDMTD phase target");
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}
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phase = measure_ddmdt_phase();
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}
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Ok(())
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}
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fn calibrate_sysref_target(rising_average: i32, falling_average: i32) -> Result<i32, &'static str> {
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let coarse_target = (falling_average - 16 + DDMTD_N) % DDMTD_N; // HACK
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info!("SYSREF calibration coarse target: {}", coarse_target);
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reach_sysref_ddmtd_target(coarse_target, 2)?;
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let target = measure_ddmdt_phase();
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info!("SYSREF calibrated target: {}", target);
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Ok(target)
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}
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fn sysref_get_sample() -> Result<bool, &'static str> {
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if sysref_sh_error() {
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return Err("SYSREF failed S/H timing");
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}
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let ret = unsafe { csr::sysref_sampler::sample_result_read() } != 0;
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Ok(ret)
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}
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fn sysref_slip_rtio_cycle() {
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for _ in 0..hmc7043::FPGA_CLK_DIV {
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hmc7043::sysref_slip();
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}
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}
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pub fn sysref_rtio_align() -> Result<(), &'static str> {
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let mut previous_sample = sysref_get_sample()?;
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let mut nslips = 0;
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loop {
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sysref_slip_rtio_cycle();
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let sample = sysref_get_sample()?;
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if sample && !previous_sample {
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info!("SYSREF aligned with RTIO TSC");
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return Ok(())
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}
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previous_sample = sample;
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nslips += 1;
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if nslips > hmc7043::SYSREF_DIV/hmc7043::FPGA_CLK_DIV {
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return Err("failed to find SYSREF transition aligned with RTIO TSC");
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}
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}
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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test_slip_ddmtd()?;
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let sysref_sh_limits = measure_sysref_sh_limits()?;
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let rising_average = average_phases(&sysref_sh_limits.rising_phases, SYSREF_SH_MOD);
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let falling_average = average_phases(&sysref_sh_limits.falling_phases, SYSREF_SH_MOD);
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let rising_max_deviation = max_phase_deviation(rising_average, &sysref_sh_limits.rising_phases);
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let falling_max_deviation = max_phase_deviation(falling_average, &sysref_sh_limits.falling_phases);
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let rising_average = rising_average >> SYSREF_SH_PRECISION_SHIFT;
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let falling_average = falling_average >> SYSREF_SH_PRECISION_SHIFT;
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let rising_max_deviation = rising_max_deviation >> SYSREF_SH_PRECISION_SHIFT;
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let falling_max_deviation = falling_max_deviation >> SYSREF_SH_PRECISION_SHIFT;
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info!("SYSREF S/H average limits (DDMTD phases): {} {}", rising_average, falling_average);
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info!("SYSREF S/H maximum limit deviation: {} {}", rising_max_deviation, falling_max_deviation);
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if rising_max_deviation > 4 || falling_max_deviation > 4 {
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return Err("excessive SYSREF S/H limit deviation");
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}
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let entry = config::read_str("sysref_ddmtd_phase_fpga", |r| r.map(|s| s.parse()));
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let target_phase = match entry {
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Ok(Ok(phase)) => {
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info!("using FPGA SYSREF DDMTD phase target from config: {}", phase);
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phase
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}
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_ => {
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let phase = calibrate_sysref_target(rising_average, falling_average)?;
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if let Err(e) = config::write_int("sysref_ddmtd_phase_fpga", phase as u32) {
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error!("failed to update FPGA SYSREF DDMTD phase target in config: {}", e);
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}
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phase
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}
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};
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reach_sysref_ddmtd_target(target_phase, 1)?;
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if sysref_sh_error() {
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return Err("SYSREF does not meet S/H timing at DDMTD phase target");
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}
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sysref_rtio_align()?;
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Ok(())
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}
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@ -120,12 +318,15 @@ pub fn sysref_auto_dac_align() -> Result<(), &'static str> {
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// We assume that DAC SYSREF traces are length-matched so only one phase
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// value is needed, and we use DAC-0 as calibration reference.
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let entry = config::read_str("sysref_phase_dac", |r| r.map(|s| s.parse()));
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let entry = config::read_str("sysref_7043_phase_dac", |r| r.map(|s| s.parse()));
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let phase = match entry {
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Ok(Ok(phase)) => phase,
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Ok(Ok(phase)) => {
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info!("using DAC SYSREF phase from config: {}", phase);
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phase
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},
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_ => {
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let phase = sysref_cal_dac(0)?;
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if let Err(e) = config::write_int("sysref_phase_dac", phase as u32) {
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if let Err(e) = config::write_int("sysref_7043_phase_dac", phase as u32) {
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error!("failed to update DAC SYSREF phase in config: {}", e);
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}
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phase
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