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urukul: expand attenuator HITL unittests

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* read back with cleared backing state
* individual channel settings
* check backing state

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-12-04 15:36:24 +00:00
parent cc143d5fec
commit baf88050fd
2 changed files with 37 additions and 4 deletions
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5
artiq/coredevice/urukul.py
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@ -138,8 +138,9 @@ class CPLD:
:param rf_sw: Initial CPLD RF switch register setting (default: 0x0).
Knowledge of this state is not transferred between experiments.
:param att: Initial attenuator setting shift register (default:
0x00000000). See also: :meth:`set_all_att_mu`. Knowledge of this state
is not transferred between experiments.
0x00000000). See also :meth:`get_att_mu` which retrieves the hardware
state without side effects. Knowledge of this state is not transferred
between experiments.
:param sync_div: SYNC_IN generator divider. The ratio between the coarse
RTIO frequency and the SYNC_IN generator frequency (default: 2 if
`sync_device` was specified).

36
artiq/test/coredevice/test_urukul.py
View File

@ -69,11 +69,37 @@ class UrukulExp(EnvExperiment):
def att(self):
self.core.break_realtime()
self.dev.init()
# clear backing state
self.dev.att_reg = 0
att_set = 0x12345678
self.dev.set_all_att_mu(att_set)
# confirm that we can set all attenuators and read back
att_get = self.dev.get_att_mu()
# confirm backing state
att_reg = self.dev.att_reg
self.set_dataset("att_set", att_set)
self.set_dataset("att_get", att_get)
self.set_dataset("att_reg", att_reg)
@kernel
def att_channel(self):
self.core.break_realtime()
self.dev.init()
# clear backing state
self.dev.att_reg = 0
att_set = int32(0x87654321)
# set individual attenuators
self.dev.set_att_mu(0, 0x21)
self.dev.set_att_mu(1, 0x43)
self.dev.set_att_mu(2, 0x65)
self.dev.set_att_mu(3, 0x87)
# confirm that we can set all attenuators and read back
att_get = self.dev.get_att_mu()
# confirm backing state
att_reg = self.dev.att_reg
self.set_dataset("att_set", att_set)
self.set_dataset("att_get", att_get)
self.set_dataset("att_reg", att_reg)
@kernel
def att_speed(self):
@ -140,8 +166,14 @@ class UrukulTest(ExperimentCase):
def test_att(self):
self.execute(UrukulExp, "att")
att_set = self.dataset_mgr.get("att_set")
att_get = self.dataset_mgr.get("att_get")
self.assertEqual(att_set, att_get)
self.assertEqual(att_set, self.dataset_mgr.get("att_get"))
self.assertEqual(att_set, self.dataset_mgr.get("att_reg"))
def test_att_channel(self):
self.execute(UrukulExp, "att_channel")
att_set = self.dataset_mgr.get("att_set")
self.assertEqual(att_set, self.dataset_mgr.get("att_get"))
self.assertEqual(att_set, self.dataset_mgr.get("att_reg"))
def test_att_speed(self):
self.execute(UrukulExp, "att_speed")