forked from M-Labs/artiq
kasli_sawgmaster: correctly tune DDS and SAWG
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@ -89,7 +89,8 @@ for i in range(4):
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 26, # 975MHz sample rate
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"pll_n": 16, # 600MHz sample rate
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"pll_vco": 2,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i)
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@ -17,6 +17,13 @@ class SinesUrukulSayma(EnvExperiment):
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@kernel
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def run(self):
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f = 9*MHz
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dds_ftw = self.urukul_chs[0].frequency_to_ftw(f)
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sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
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if dds_ftw != sawg_ftw:
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print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
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return
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# Note: when testing sync, do not reboot Urukul, as it is not
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# synchronized to the FPGA (yet).
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self.core.reset()
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@ -24,7 +31,7 @@ class SinesUrukulSayma(EnvExperiment):
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for urukul_ch in self.urukul_chs:
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delay(1*ms)
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urukul_ch.init()
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urukul_ch.set(9*MHz, amplitude=0.5)
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urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
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urukul_ch.set_att(6.)
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urukul_ch.sw.on()
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@ -43,7 +50,7 @@ class SinesUrukulSayma(EnvExperiment):
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.amplitude1.set(.4)
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sawg.frequency0.set(9*MHz)
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sawg.frequency0.set_mu(sawg_ftw)
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while self.drtio_is_up():
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pass
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