3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
051a14abf2
rtio/dma: fix endianness
2021-09-10 13:25:12 +08:00
a833974b50
analyzer: fix endianness
2021-09-10 13:25:12 +08:00
fc42d053d9
kernel: use vexriscv
2021-09-10 13:25:12 +08:00
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
Mikołaj Sowiński
898122f3e5
Added support for HVAMP_8CH ( #1741 )
2021-08-16 13:39:00 +08:00
7879d3630b
made kc705/gtx interface more similar to kasli/gtp
2021-08-10 18:53:52 +08:00
242dfae38e
kc705: fix DRTIO targets
2021-08-06 15:41:47 +08:00
dc546630e4
kc705: DRTIO variants WIP
2021-08-06 14:41:41 +08:00
fd824f7ad0
ddb_template: print LED channel nos on Kasli v2
2021-08-05 17:29:38 +02:00
ea0c7b6173
Merge remote-tracking branch 'harrydrtio/k7-drtio'
2021-06-15 10:04:45 +08:00
Star Chen
9dee8bb9c9
Kasli: Added front panel user LED ( #1623 ) ( #1694 )
2021-06-07 16:05:50 +08:00
92fd705990
increase memory allocated to comms CPU
...
See discussion in #1612 .
2021-02-21 19:06:12 +08:00
d33a206f04
eem: fix Urukul QSPI after 9ef5717de8 (2)
2021-02-12 13:17:48 +08:00
22ce5b0299
eem: fix Urukul QSPI after 9ef5717de8
2021-02-12 10:59:53 +08:00
e54dd08821
metlino,sayma: adapt to new EEM API
...
This also enables 4X SERDES TTLs.
2021-02-10 15:32:10 +08:00
547254e89e
eem_7series: pass through kwargs
2021-02-10 15:31:49 +08:00
49299c00a9
eem: enable DCI for LVDS TTL
2021-02-10 15:31:25 +08:00
9ef5717de8
eem: support different I/O standards in EEM slots
2021-02-10 15:31:05 +08:00
461199b903
kasli_generic: warn if min_artiq_version is not met
2021-02-10 15:26:15 +08:00
cf9cf0ab6f
ttl_serdes_7series: add dci (HP bank) support
2021-02-07 22:32:18 +08:00
997a48fb31
ttl_serdes_ultrascale: fix, add dummy dci argument
2021-02-07 22:31:46 +08:00
bbe0c9162a
ttl_serdes_ultrascale: cleanup
2021-02-07 22:00:33 +08:00
3572e2a9c7
ttl_serdes_7series: fix
2021-02-07 21:41:13 +08:00
88c212b84f
ttl_serdes_7series: cleanup
2021-02-07 21:33:21 +08:00
db25f4e8f7
ttl_serdes_7series: use simpler I/O buffers
...
In theory equivalent with these parameters.
2021-02-07 20:10:37 +08:00
6bd9691ba8
gateware: remove TTL dead code
2021-02-07 19:58:02 +08:00
bfacd1e5b3
eem: fix Grabber cc_0-2 signal definitions
2021-02-07 18:01:05 +08:00
f7a33a1f99
gateware: make 7-series EEM handling functions shareable
2021-02-07 14:34:26 +08:00
a0fd5261ea
kc705: cleanup
2021-01-22 11:11:13 +08:00
7c4eed7a11
kc705: simplify DRTIO master & satellite
...
* KC705 master: user can no longer choose whether or not the SMA acts as the 2nd DRTIO channel; SFP and SMA now act as the 1st and 2nd channel respectively by default.
* KC705 satellite: user should now use `--sma` to enable using the SMA as the satellite channel; SFP acts as the satellite channel by default.
2021-01-22 11:11:13 +08:00
88b14082b6
drtio/transceiver/gtx: delete obsolete modules
2021-01-20 15:05:32 +08:00
9daf77bd58
kc705: add multichannel support on satellite
...
* Two DRTIO channels (i.e. satellite and repeater) are enabled by default.
* User can choose either the SFP or SMA as the satellite channel (by passing `--drtio-sat sfp` or --drtio-sat sma` to the argparser), and the unchosen would become the repeater channel.
2021-01-20 15:05:32 +08:00
52afd4ef6b
kc705: add GTX multilane support, add multichannel support on master
...
* One DRTIO master channel is enabled by default.
* User can set the SMA as the 2nd master channel (by passing --drtio-sma to the argparser).
* Multi-channel (i.e. with repeaters) on KC705 satellite is supported but has not been implemented yet.
2021-01-20 15:05:32 +08:00
f6d39fd6ba
kc705: revive DRTIO master with updated syntax
...
* KC705 master variant now uses Si5324 as synthesiser.
* Multi-channel has not been implemented yet.
2021-01-20 15:05:31 +08:00
f25e86e934
kc705: revive DRTIO satellite with updated syntax, update GTX
...
* Multi-channel has not been implemented yet.
2021-01-20 11:25:38 +08:00
c675488a99
reorganize JSON schema files
2021-01-16 10:43:14 +08:00
c6807f4594
kasli_generic: validate description against schema, use defaults from schema
2021-01-16 10:35:23 +08:00
45b5cfce05
gateware: add a kasli_generic.schema.json
2021-01-16 10:35:23 +08:00
cff7bcc122
Merge branch 'master' ( 43be383c86) into k7-drtio
2020-12-31 13:30:46 +08:00
dc7addf394
Revert "drtio: remove KC705/GTX support"
...
This reverts commit ebdbaaad32
2020-12-31 13:29:50 +08:00
43ecb3fea6
sayma: add comments about CPLL line rate on KU GTH
2020-12-19 17:05:20 +08:00
8cd794e9f4
jesd204_tools: use new syntax from jesd204b core
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* requires jesd204b changes as in https://github.com/HarryMakes/jesd204b/tree/gth
2020-12-19 17:05:20 +08:00
ccdc741e73
sayma_amc: fix --sfp argument
2020-12-07 18:02:36 +08:00
ea95d91428
wrpll: separate collector reset
2020-11-09 17:57:13 +08:00
a9dd0a268c
Merge pull request #1533 from m-labs/phaser
...
Phaser
2020-10-19 09:30:12 +02:00
30d1acee9f
fastlink: fix fastino style link
2020-10-18 20:43:21 +00:00
d98357051c
add ref data
2020-10-18 20:43:21 +00:00
139385a571
fastlink: add fastino test
2020-10-18 17:11:09 +00:00
d185f1ac67
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00
3f076bf79b
wrpll: fix mulshift
2020-10-16 22:05:37 +08:00
hartytp
a058be2ede
wrpll: fix test_helper_collector
2020-10-08 19:43:12 +08:00
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
07d43b6e5f
wrpll: babysit Vivado DSP retiming
...
Design now passes timing.
2020-10-08 17:51:27 +08:00
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
...
We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
...
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
...
TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
hartytp
b44b870452
wrpll.filters: update to match Weida's MatLab simulations
2020-10-08 15:32:27 +08:00
hartytp
e9ab434fa7
wrpll.core: update for modified collector
2020-10-08 15:32:27 +08:00
17c952b8fb
wrpll: style
2020-10-08 15:32:27 +08:00
hartytp
ebb7ccbfd1
wrpll: document DDMTD collector and fix unwrapping
2020-10-08 15:32:27 +08:00
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
c55f2222dc
fastino: documentation and eem pass-through
...
* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
29c940f4e3
kasli2: forward sma_clkin to si5324
2020-09-17 16:53:43 +08:00
868a9a1f0c
phaser: new multidds
2020-09-16 14:06:38 +00:00
c18f515bf9
phaser: rework rtio channels, sync_dly, init()
2020-09-16 12:23:07 +00:00
fdd2d6f2fb
phaser: SI methods
2020-09-12 11:02:37 +00:00
4e24700205
phaser: spelling
2020-09-09 16:52:52 +00:00
8aaeaa604e
phaser: share_lut
2020-09-07 16:06:35 +00:00
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
dfbf3311cb
sayma_amc: add support for 4x DIO output channels via FMC
2020-08-31 16:21:45 +08:00
1ad9deaf91
fmcdio_vhdci_eem: fix pin naming
2020-08-31 16:21:45 +08:00
45ae6202c0
build_soc: add identifier_str override option
...
Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
272dc5d36a
phaser: documentation
2020-08-28 16:36:44 +00:00
96fc248d7c
phaser: synchronize multidds to frame
2020-08-27 14:28:19 +00:00
c10ac2c92a
phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb)
2020-08-27 14:26:09 +00:00
e5e2392240
phaser: wire up multidds
2020-08-26 17:12:41 +00:00
d1be1212ab
phaser: coredevice shim, dds [wip]
2020-08-26 15:10:50 +00:00
20fcfd95e9
phaser: coredevice shim, readback fix
2020-08-24 15:46:31 +00:00
bcefb06e19
phaser: ddb template, split crc
2020-08-24 14:51:50 +00:00
11c9def589
phaser: readback delay, test fastlink
2020-08-24 14:49:36 +00:00
63e4b95325
fastlink: rework crc injection
2020-08-23 19:41:13 +00:00
a27a03ab3c
fastlink: fix crc vs data width
2020-08-23 19:02:50 +00:00
7e584d0da1
fastino: use fastlink
2020-08-22 11:56:23 +00:00
3e99f1ce5a
phaser: refactor link
2020-08-22 11:56:23 +00:00
a34a647ec4
phaser: refactor fastlink
2020-08-22 11:56:23 +00:00
aa0154d8e2
phaser: initial
2020-08-22 11:56:23 +00:00
504f72a02c
rtio: remove legacy i_overflow_reset CSR
2020-08-06 17:52:32 +08:00
