forked from M-Labs/artiq
kernel: use vexriscv
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@ -1,7 +1,7 @@
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import wishbone
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from misoc.cores import mor1kx
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from misoc.cores import vexriscv
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from misoc.integration.wb_slaves import WishboneSlaveManager
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@ -23,9 +23,9 @@ class KernelCPU(Module):
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self.cd_sys_kernel.rst.eq(self._reset.storage)
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]
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self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
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mor1kx.MOR1KX(
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vexriscv.VexRiscv(
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platform,
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OPTION_RESET_PC=exec_address))
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exec_address))
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# DRAM access
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self.wb_sdram = wishbone.Interface()
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