forked from M-Labs/artiq
analyzer: fix endianness
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d623acc29d
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@ -42,6 +42,20 @@ assert layout_len(exception_layout) == message_len
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assert layout_len(stopped_layout) == message_len
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def convert_signal(signal):
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assert len(signal) % 8 == 0
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nbytes = len(signal)//8
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assert nbytes % 4 == 0
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nwords = nbytes//4
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signal_words = []
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for i in range(nwords):
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signal_bytes = []
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for j in range(4):
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signal_bytes.append(signal[8*(j+i*4):8*((j+i*4)+1)])
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signal_words.extend(reversed(signal_bytes))
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return Cat(*signal_words)
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class MessageEncoder(Module, AutoCSR):
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def __init__(self, tsc, cri, enable):
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self.source = stream.Endpoint([("data", message_len)])
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@ -161,7 +175,7 @@ class DMAWriter(Module, AutoCSR):
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membus.stb.eq(self.sink.stb),
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self.sink.ack.eq(membus.ack),
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membus.we.eq(1),
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membus.dat_w.eq(self.sink.data)
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membus.dat_w.eq(convert_signal(self.sink.data))
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]
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if messages_per_dw > 1:
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for i in range(dw//8):
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