forked from M-Labs/artiq
targets: default to vexriscv cpu
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1b516b16e2
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@ -116,7 +116,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -298,7 +298,7 @@ class MasterBase(MiniSoC, AMPSoC):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -474,7 +474,7 @@ class SatelliteBase(BaseSoC):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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**kwargs)
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@ -172,7 +172,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -249,7 +249,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -382,7 +382,7 @@ class _SatelliteBase(BaseSoC):
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def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -42,7 +42,7 @@ class Master(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -56,7 +56,7 @@ class SatelliteBase(MiniSoC):
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -77,7 +77,7 @@ class _SatelliteBase(BaseSoC):
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def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="vexriscv",
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**kwargs)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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self.rtio_clk_freq = rtio_clk_freq
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