forked from M-Labs/artiq
kc705: simplify DRTIO master & satellite
* KC705 master: user can no longer choose whether or not the SMA acts as the 2nd DRTIO channel; SFP and SMA now act as the 1st and 2nd channel respectively by default. * KC705 satellite: user should now use `--sma` to enable using the SMA as the satellite channel; SFP acts as the satellite channel by default.
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@ -30,7 +30,7 @@ class Master(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, drtio_sma=False, **kwargs):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -52,11 +52,12 @@ class Master(MiniSoC, AMPSoC):
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = [platform.request("sfp_tx")]
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rx_pads = [platform.request("sfp_rx")]
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if drtio_sma:
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tx_pads.append(platform.request("user_sma_mgt_tx"))
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rx_pads.append(platform.request("user_sma_mgt_rx"))
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tx_pads = [
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platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
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]
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rx_pads = [
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platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
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]
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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@ -169,14 +170,9 @@ def main():
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builder_args(parser)
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soc_kc705_args(parser)
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parser.set_defaults(output_dir="artiq_kc705/master")
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parser.add_argument("--drtio-sma", default=False, action="store_true",
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help="use the SMA connectors (RX: J17, J18, TX: J19, J20) as 2nd DRTIO channel")
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args = parser.parse_args()
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argdict = dict()
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argdict["drtio_sma"] = args.drtio_sma
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soc = Master(**soc_kc705_argdict(args), **argdict)
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soc = Master(**soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -31,15 +31,13 @@ class Satellite(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, drtio_sat="sfp", **kwargs):
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def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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**kwargs)
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assert drtio_sat in ["sfp", "sma"]
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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@ -58,7 +56,7 @@ class Satellite(BaseSoC):
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rx_pads = [
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platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
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]
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if drtio_sat == "sma":
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if sma_as_sat:
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tx_pads = tx_pads[::-1]
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rx_pads = rx_pads[::-1]
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@ -184,13 +182,13 @@ def main():
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builder_args(parser)
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soc_kc705_args(parser)
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parser.set_defaults(output_dir="artiq_kc705/satellite")
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parser.add_argument("--drtio-sat", default="sfp",
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help="use the SFP or the SMA connectors (RX: J17, J18, TX: J19, J20) "
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"as DRTIO satellite channel (choices: sfp, sma; default: sfp)")
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parser.add_argument("--sma", default=False, action="store_true",
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help="use the SMA connectors (RX: J17, J18, TX: J19, J20) "
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"as DRTIO satellite channel instead of the SFP")
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args = parser.parse_args()
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argdict = dict()
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argdict["drtio_sat"] = args.drtio_sat
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argdict["sma_as_sat"] = args.sma
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soc = Satellite(**soc_kc705_argdict(args), **argdict)
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build_artiq_soc(soc, builder_argdict(args))
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