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made kc705/gtx interface more similar to kasli/gtp

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mwojcik 2021-08-09 15:55:28 +02:00 committed by Sébastien Bourdeauducq
parent 242dfae38e
commit 7879d3630b
2 changed files with 15 additions and 25 deletions
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17
artiq/gateware/drtio/transceiver/gtx_7series.py
View File

@ -16,7 +16,7 @@ class GTX_20X(Module):
# * GTX PLL frequency @ 2.5GHz
# * GTX line rate (TX & RX) @ 2.5Gb/s
# * GTX TX/RX USRCLK @ 125MHz == coarse RTIO frequency
def __init__(self, refclk, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq=125e6, tx_mode="single", rx_mode="single"):
def __init__(self, refclk, pads, sys_clk_freq, rtio_clk_freq=125e6, tx_mode="single", rx_mode="single"):
assert tx_mode in ["single", "master", "slave"]
assert rx_mode in ["single", "master", "slave"]
@ -229,10 +229,10 @@ class GTX_20X(Module):
p_RXCDR_LOCK_CFG=0b010101,
# Pads
i_GTXRXP=rx_pads.p,
i_GTXRXN=rx_pads.n,
o_GTXTXP=tx_pads.p,
o_GTXTXN=tx_pads.n,
i_GTXRXP=pads.rxp,
i_GTXRXN=pads.rxn,
o_GTXTXP=pads.txp,
o_GTXTXN=pads.txn,
# Other parameters
p_PCS_RSVD_ATTR=(
@ -282,9 +282,8 @@ class GTX_20X(Module):
class GTX(Module, TransceiverInterface):
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq=125e6, master=0):
assert len(tx_pads) == len(rx_pads)
self.nchannels = nchannels = len(tx_pads)
def __init__(self, clock_pads, pads, sys_clk_freq, rtio_clk_freq=125e6, master=0):
self.nchannels = nchannels = len(pads)
self.gtxs = []
self.rtio_clk_freq = rtio_clk_freq
@ -307,7 +306,7 @@ class GTX(Module, TransceiverInterface):
else:
mode = "master" if i == master else "slave"
# Note: RX phase alignment is to be done on individual lanes, not multi-lane.
gtx = GTX_20X(refclk, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq=rtio_clk_freq, tx_mode=mode, rx_mode="single")
gtx = GTX_20X(refclk, pads[i], sys_clk_freq, rtio_clk_freq=rtio_clk_freq, tx_mode=mode, rx_mode="single")
# Fan-out (to slave) / Fan-in (from master) of the TXUSRCLK
if mode == "slave":
self.comb += gtx.cd_rtio_tx.clk.eq(rtio_tx_clk)

23
artiq/gateware/targets/kc705.py
View File

@ -271,18 +271,14 @@ class _MasterBase(MiniSoC, AMPSoC):
platform.add_extension(_ams101_dac)
self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
tx_pads = [
platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
]
rx_pads = [
platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
data_pads = [
platform.request("sfp"), platform.request("user_sma_mgt")
]
# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("si5324_clkout"),
tx_pads=tx_pads,
rx_pads=rx_pads,
pads=data_pads,
sys_clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
@ -405,21 +401,16 @@ class _SatelliteBase(BaseSoC):
platform.add_extension(_ams101_dac)
self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
tx_pads = [
platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
]
rx_pads = [
platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
data_pads = [
platform.request("sfp"), platform.request("user_sma_mgt")
]
if sma_as_sat:
tx_pads = tx_pads[::-1]
rx_pads = rx_pads[::-1]
data_pads = data_pads[::-1]
# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("si5324_clkout"),
tx_pads=tx_pads,
rx_pads=rx_pads,
pads=data_pads,
sys_clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")