srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

ttl_serdes_ultrascale: cleanup

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2021-02-07 22:00:29 +08:00
parent 3572e2a9c7
commit bbe0c9162a
1 changed files with 30 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
artiq/gateware/rtio/phy/ttl_serdes_ultrascale.py
View File

@ -4,7 +4,8 @@ from artiq.gateware.rtio.phy import ttl_serdes_generic
class _OSERDESE3(Module):
def __init__(self, dw, pad, pad_n=None):
def __init__(self, dw):
self.ser_out = Signal()
self.o = Signal(dw)
self.t_in = Signal()
self.t_out = Signal()
@ -16,23 +17,15 @@ class _OSERDESE3(Module):
p_DATA_WIDTH=dw, p_INIT=0,
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=pad_o, o_T_OUT=self.t_out,
o_OQ=self.ser_out, o_T_OUT=self.t_out,
i_RST=ResetSignal("rtio"),
i_CLK=ClockSignal("rtiox"), i_CLKDIV=ClockSignal("rtio"),
i_D=self.o, i_T=self.t_in)
if pad_n is None:
self.comb += pad.eq(pad_o)
else:
self.specials += Instance("IOBUFDS_INTERMDISABLE",
i_IBUFDISABLE=1,
i_INTERMDISABLE=1,
i_I=pad_o,
i_T=self.t_out,
io_IO=pad, io_IOB=pad_n)
class _ISERDESE3(Module):
def __init__(self, dw, pad, pad_n=None):
def __init__(self, dw):
self.ser_in = Signal()
self.o = Signal(dw)
self.i = Signal(dw)
self.oe = Signal()
@ -45,21 +38,13 @@ class _ISERDESE3(Module):
p_IS_CLK_B_INVERTED=1,
p_DATA_WIDTH=dw,
i_D=pad_i,
i_D=self.ser_in,
i_RST=ResetSignal("rtio"),
i_FIFO_RD_EN=0,
i_CLK=ClockSignal("rtiox"),
i_CLK_B=ClockSignal("rtiox"), # locally inverted
i_CLKDIV=ClockSignal("rtio"),
o_Q=Cat(*[self.i[i] for i in reversed(range(dw))]))
if pad_n is None:
self.comb += pad_i.eq(pad)
else:
self.specials += Instance("IBUFDS_INTERMDISABLE",
i_IBUFDISABLE=0,
i_INTERMDISABLE=0,
o_O=pad_i,
io_I=pad, io_IB=pad_n)
class _IOSERDESE3(Module):
@ -70,26 +55,17 @@ class _IOSERDESE3(Module):
# # #
pad_i = Signal()
pad_o = Signal()
iserdes = _ISERDESE3(dw, pad_i)
oserdes = _OSERDESE3(dw, pad_o)
iserdes = _ISERDESE3(dw)
oserdes = _OSERDESE3(dw)
self.submodules += iserdes, oserdes
if pad_n is None:
self.specials += Instance("IOBUF",
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad)
else:
self.specials += Instance("IOBUFDS_INTERMDISABLE",
i_IBUFDISABLE=~oserdes.t_out,
i_INTERMDISABLE=~oserdes.t_out,
i_I=pad_o, o_O=pad_i, i_T=oserdes.t_out,
io_IO=pad, io_IOB=pad_n)
self.comb += [
self.i.eq(iserdes.i),
oserdes.t_in.eq(~self.oe),
oserdes.o.eq(self.o)
]
self.ser_out = oserdes.ser_out
self.ser_in = iserdes.ser_in
self.t_out = oserdes.t_out
class Output(ttl_serdes_generic.Output):
@ -98,9 +74,28 @@ class Output(ttl_serdes_generic.Output):
self.submodules += serdes
ttl_serdes_generic.Output.__init__(self, serdes)
if pad_n is None:
self.comb += pad.eq(serdes.ser_out)
else:
self.specials += Instance("IOBUFDS",
i_I=serdes.ser_out,
i_T=serdes.t_out,
io_IO=pad, io_IOB=pad_n)
class InOut(ttl_serdes_generic.InOut):
def __init__(self, dw, pad, pad_n=None):
serdes = _IOSERDESE3(dw, pad, pad_n)
self.submodules += serdes
ttl_serdes_generic.InOut.__init__(self, serdes)
if pad_n is None:
self.specials += Instance("IOBUF",
i_I=serdes.ser_out, o_O=serdes.ser_in, i_T=serdes.t_out,
io_IO=pad)
else:
self.specials += Instance("IOBUFDS_INTERMDISABLE",
i_IBUFDISABLE=~serdes.t_out,
i_INTERMDISABLE=~serdes.t_out,
i_I=serdes.ser_out, o_O=serdes.ser_in, i_T=serdes.t_out,
io_IO=pad, io_IOB=pad_n)