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523 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 9ab63920e0 Remove Pipistrello support 
Closes #658
Closes #381
 2017-05-15 17:17:44 +08:00
Robert Jördens 170d2886fd Merge branch 'pdq' 
* pdq:
  pdq: documentation
  pdq2 -> pdq
  pdq2: use 16 bit data, buffered read_mem()
  spi: style
  pdq2: mem_read
  pdq2: align subsequent writes to end
  sma_spi: undo cri_con
  pdq2: memory write, kernel_invariants
  sma_spi: cri/cd changes
  sma_spi: LVCMOS25
  coredevice.spi: kernel invariants and style
  sma_spi: free up user_sma pins
  sma_spi: add demo target with SPI on four SMA
  pdq2: memory write
  pdq2: crc/frame register accessors
  doc: pdq2 spi backend
  pdq2: config writes
 2017-05-12 11:46:45 +02:00
Florent Kermarrec 79c339d4ac gateware/targets/phaser: jesd core now handles jsync completely 2017-04-26 22:25:08 +02:00
Florent Kermarrec 0546affd4c gateware/target/phaser: jesd start signal renamed to jsync 2017-04-26 12:27:40 +02:00
Robert Jördens ed8edf318d sma_spi: undo cri_con 2017-04-08 17:19:35 +02:00
Robert Jördens 16b7f8f50c sma_spi: cri/cd changes 2017-04-08 17:16:19 +02:00
Robert Jördens 1e6e81a19e sma_spi: LVCMOS25 2017-04-08 17:16:19 +02:00
Robert Jördens 555b3c38c1 sma_spi: free up user_sma pins 2017-04-08 17:16:19 +02:00
Robert Jördens 2c7c6143ab sma_spi: add demo target with SPI on four SMA 2017-04-08 17:16:19 +02:00
Sebastien Bourdeauducq c2667debf8 drtio: test replace in RTL simulation 2017-04-06 16:33:59 +08:00
Sebastien Bourdeauducq 729e7b52f0 drtio: collision/replace fixes 2017-04-06 16:33:49 +08:00
Sebastien Bourdeauducq 83d87b5805 drtio: remove outdated comment 2017-04-06 12:45:10 +08:00
Sebastien Bourdeauducq c0100ebc56 rtio: fix indentation 2017-04-06 12:08:13 +08:00
Sebastien Bourdeauducq 207453efcd rtio: add a missing case for collision reporting 2017-04-06 11:28:16 +08:00
Sebastien Bourdeauducq 674bf82f3a gateware: add cri_con CSRs to all DMA-capable targets 2017-04-06 01:14:09 +08:00
Sebastien Bourdeauducq 5e3aef45dc drtio: support collision/replace + detect sequence errors at satellite 2017-04-06 01:06:56 +08:00
whitequark 17b5388259 gateware: remove one stray CRI arbiter remnant. 2017-04-05 16:38:56 +00:00
whitequark 464202d0aa gateware: connect CRI switch to kernel CPU. 2017-04-05 16:10:53 +00:00
whitequark 47632f81b1 gateware: CRIArbiter -> CRISwitch. 2017-04-05 16:10:39 +00:00
whitequark 391660e545 gateware: simplify the CRI arbiter to use a plain mux. 2017-04-05 15:09:19 +00:00
Sebastien Bourdeauducq 12249dac57 rtio: do not clear asynchronous error flags on RTIO reset 2017-04-03 00:20:30 +08:00
Sebastien Bourdeauducq db3118b916 drtio: use BlindTransfer for error reporting 2017-04-03 00:18:07 +08:00
Sebastien Bourdeauducq 8c414cebc7 drtio: report busy errors 2017-04-03 00:11:08 +08:00
Sebastien Bourdeauducq 008678b741 drtio: add infrastructure for reporting busy/collision errors 2017-04-02 23:45:55 +08:00
Sebastien Bourdeauducq 0a687b7902 drtio: report satellite errors through firmware 2017-04-01 12:18:00 +08:00
Sebastien Bourdeauducq 28211e0b32 gateware: reset RTIO DMA core when kernel CPU is reset 2017-03-31 15:35:28 +08:00
Sebastien Bourdeauducq 200c499114 test: change base address in DMA simulation testbench 2017-03-31 13:17:00 +08:00
Sebastien Bourdeauducq ea3af1e20e drtio: remove obsolete CSR accesses from test 2017-03-27 16:44:22 +08:00
Sebastien Bourdeauducq b74d6fb9ba make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
whitequark 4de336fbe9 gateware: reverse bytes of SDRAM word, not bits. 2017-03-17 11:16:46 +00:00
whitequark 6b63322106 gateware: reverse SDRAM words in RTIO DMA engine. 2017-03-17 07:29:28 +00:00
whitequark 4b14887ddb gateware: work around ISE/Vivado bugs with very wide shifts. 2017-03-17 07:29:28 +00:00
whitequark 4beda73217 firmware: don't build libdyld through misoc. 2017-03-14 08:33:31 +00:00
Sebastien Bourdeauducq a7de58b604 rtio: Inout → InOut 2017-03-14 14:18:55 +08:00
Sebastien Bourdeauducq 13ae1d1a38 drtio: input unittest 2017-03-14 14:14:55 +08:00
Sebastien Bourdeauducq 56fd9b3b4b drtio: input fixes 2017-03-14 14:14:43 +08:00
Sebastien Bourdeauducq 95ede18809 drtio: support PHY latency compensation 2017-03-14 00:01:38 +08:00
Sebastien Bourdeauducq 497c795d8c drtio: input support (untested) 2017-03-13 23:54:44 +08:00
Sebastien Bourdeauducq d1b9f9d737 drtio: rt_packets → rt_packet 2017-03-13 00:10:07 +08:00
Sebastien Bourdeauducq 6b7c781ff2 drtio: introduce 'standard request' interface in RT packet layer 2017-03-13 00:08:03 +08:00
Sebastien Bourdeauducq 2b8729f326 drtio: clear any read request on satellite reset 2017-03-13 00:00:38 +08:00
Sebastien Bourdeauducq 1e47e638bb drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
Sebastien Bourdeauducq 1e6a33b586 rtio: handle input timeout in gateware 
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
 2017-03-03 17:37:47 +08:00
Sebastien Bourdeauducq d2f2415b50 analyzer: use CRI and connect at RTIO core 
This causes DMA events to be included in analyzer traces.
 2017-03-02 18:47:56 +08:00
Sebastien Bourdeauducq 7d6ebabc1b reorganize core device communication code 2017-02-27 18:37:30 +08:00
Sebastien Bourdeauducq f017d1771f gateware: remove unused configs in targets (not needed with new moninj) 2017-02-25 12:14:56 +08:00
Sebastien Bourdeauducq 360be0098f drtio: map local RTIO core on lower channels 2017-02-24 18:15:27 +08:00
Sebastien Bourdeauducq b455ea447d gateware: add moninj to drtio targets 2017-02-21 21:54:47 +08:00
Sebastien Bourdeauducq c66efc0279 moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
Robert Jördens c022b53578 kernel_cpu: enable perf counters 2017-02-18 14:09:12 +01:00