d7dd75e833
comm_kernel: fix off-by-one error for numeric value range check
2022-01-11 10:13:42 +08:00
095fb9e333
add Almazny support ( #1780 )
2022-01-11 09:55:39 +08:00
4e3e0d129c
firmware: fix compilation warning
2022-01-11 09:31:26 +08:00
12ee326fb4
firmware: fixed personality function
2022-01-11 09:30:19 +08:00
61349f9685
sinara_tester: fix outdated API
2022-01-10 17:23:28 +08:00
cea0a15e1e
suservo: use default urukul profile
2022-01-10 16:21:39 +08:00
8b45f917d1
urukul: use default profile
2022-01-10 16:21:39 +08:00
6542b65db3
compiler: fixed exception codegen issues
2022-01-10 15:54:29 +08:00
9f90088fa6
compiler: generate appropriate landingpad IR
...
When used together with modified personality function, we got ~20%
performance improvement in exception unwinding with zynq.
2022-01-10 15:54:29 +08:00
5e1847e7c1
compiler: rename variables to retainedNodes
...
Part of the changes that was made to LLVM 6 by the time that LLVM 7 was released.
LLVM commit: 2c864551dfhttps://reviews.llvm.org/D45024
2022-01-10 11:28:37 +08:00
6f3c49528d
compiler: revert cabe5ac
...
The lack of debug emitter causes #1821 .
2022-01-10 11:26:03 +08:00
02555e48a0
update NAC3, use power operator
2022-01-09 11:45:10 +08:00
eaa1505c94
update documentation ( #1820 )
2022-01-08 11:55:52 +08:00
Leon Riesebos
f42bea06a8
worker_db: removed warning for writing a dataset that is also in the archive
...
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
2022-01-08 11:48:18 +08:00
9d493028e5
gateware/suservo: write to profile 7
...
Fixes #1817 .
2022-01-07 16:41:19 +08:00
bbac477092
tools: fix importlib issue
2021-12-21 13:20:11 +08:00
088c3b470e
update NAC3, use new Kernel type annotation
2021-12-20 17:56:40 +08:00
c0a7be0a90
llvm_ir: move stacksave before lltag alloca in build_rpc
...
Signed-off-by: Steve Fan <sf@m-labs.hk>
2021-12-19 00:07:07 +00:00
9e5e234af3
stop using explicit ProactorEventLoop on Windows
...
It is now the default in Python.
2021-12-14 20:06:38 +08:00
352317df11
test_dataset_db: remove (too much breakage on Windows)
2021-12-14 19:27:15 +08:00
a518963a47
test_dataset_db: disable tests broken on windows
2021-12-14 19:19:22 +08:00
37f14d94d0
test_dataset_db: fix for windows
2021-12-14 19:07:17 +08:00
Peter Drmota
7c664142a5
Simplified use of the AD9910 RAM feature ( #1584 )
...
* coredevice: Change Urukul default single-tone profile to 7
This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode.
Signed-off-by: Peter Drmota <peter.drmota@physics.ox.ac.uk>
* ad9910/set_mu: comment on caveats when setting register
* ad9910: avoid unnecessary write/param
Credit: Solution proposed by @pmldrmota in https://github.com/m-labs/artiq/pull/1584#issuecomment-987774353
* revert 1064fdff158a7be7
2021-12-13 23:44:03 +08:00
dad23b6981
coredevice/ad53xx: use len(list)
2021-12-09 12:40:01 +08:00
33a9ca2684
tools/file_import: use SourceFileLoader
...
This allows loading modules from files with extensions not in
importlib.machinery.SOURCE_SUFFIXES
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-09 11:47:04 +08:00
1def0d98c5
Merge branch 'master' into dataset-compression
2021-12-06 12:40:30 +08:00
Leon Riesebos
7ffe4dc2e3
coredevice: set default pow for ad9912 set_mu()
2021-12-06 12:34:55 +08:00
Leon Riesebos
9e3ea4e8ef
coredevice: fixed type annotations for AD9910
2021-12-06 12:34:55 +08:00
31ac6881df
update NAC3, restore original delays
2021-12-06 12:21:52 +08:00
e34f4cc99b
language: add floor64 and ceil64
2021-12-04 20:13:00 +08:00
12c39aaaae
coredevice/adf5356: use nac3 floor/ceil
2021-12-04 19:04:48 +08:00
2059fd375e
language: add virtual
2021-12-04 19:03:39 +08:00
Steve Fan
4a6bea479a
Host report for async error upon kernel termination ( #1791 )
...
Closes #1644
2021-12-04 13:33:24 +08:00
7953f3d705
kc705: add drtio 100mhz clk switch
2021-12-03 17:19:11 +08:00
f281112779
satman: add 100mhz si5324 settings
...
siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
eec3ea6589
siphaser: add support for 100mhz rtio
2021-12-03 17:19:11 +08:00
Etienne Wodey
9f830b86c0
kasli: add SED lanes count option to HW description JSON file ( #1745 )
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-03 17:05:35 +08:00
b8e7add785
language: remove deprecated set_dataset(..., save=...)
2021-12-01 22:41:34 +08:00
6a09b92fb3
examples/nac3devices: fix mirny clocking
2021-11-29 18:15:06 +08:00
b2f7022e0a
examples/nac3devices: demonstrate new capabilities
2021-11-28 12:48:18 +08:00
e45c194c49
coredevice/adf5356: port to NAC3
2021-11-28 12:38:23 +08:00
David Nadlinger
c6039479e4
compiler: Add lit test for call site attributes [nfc]
2021-11-27 04:46:07 +00:00
David Nadlinger
63b5727a0c
compiler: Also emit byval argument attributes at call sites
...
See previous commit.
GitHub: Fixes #1599 .
2021-11-27 04:45:50 +00:00
David Nadlinger
9b01db3d11
compiler: Emit sret call site argument attributes
...
LLVM 6 seemed not to mind the mismatch, but more recent
versions produce miscompilations without this.
Needs llvmlite support (GitHub: numba/llvmlite#702 ).
2021-11-27 04:44:41 +00:00
6a433b2fce
artiq_sinara_tester: test Urukul attenuator digital control
2021-11-24 18:57:16 +08:00
5800496425
coredevice/adf5356_reg: port to NAC3
2021-11-24 16:54:58 +08:00
9423428bb0
drtio: fix crc32 offset address
2021-11-24 12:00:56 +08:00
29f42ccd8a
coredevice/mirny: port to NAC3
2021-11-23 17:13:43 +08:00
f5a5b7a22a
examples: add nac3devices
2021-11-23 16:41:29 +08:00
3a6fcd069d
remove old examples
2021-11-23 16:37:40 +08:00
d8e1a22bdf
coredevice/ad53xx: remove problematic default param
2021-11-23 16:12:36 +08:00
34789767f0
firmware: fix compilation warning
2021-11-22 18:23:28 +08:00
bd95d9cf3d
coredevice/zotino: port to NAC3
2021-11-19 19:13:50 +08:00
64877c0588
fix Python 3.9 compatibility
2021-11-19 18:18:24 +08:00
aa5f667ad8
ad9912: increase slack (no kernel invariants in NAC3 yet?)
2021-11-19 12:47:52 +08:00
cc1080e055
ad9912: fix frequency_to_ftw
2021-11-19 12:42:08 +08:00
b49f813b17
artiq_flash: ignore checking non-RTM artifacts if unused
2021-11-18 16:59:32 +08:00
f4acf04405
coredevice: fix run method
2021-11-16 18:32:14 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability ( #1500 )
...
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync
* SUServo: Wrap CPLD and DDS devices in a list
* SUServo: Refactor [nfc]
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
2021-11-15 12:09:16 +08:00
222968d68b
coredevice: reinstate AugAssign methods
2021-11-13 12:42:13 +08:00
38e554fe98
artiq_run: fix ELF handling
2021-11-12 19:57:48 +08:00
75dad8090f
Merge branch 'master' into nac3
2021-11-12 19:46:37 +08:00
95eb218112
import_cache: read files only once
2021-11-11 20:42:49 +08:00
1ea3cf48d6
fix core.run invokation
2021-11-11 20:35:45 +08:00
5a3bf4894f
reinstate import_cache hack ( #416 )
2021-11-11 20:35:06 +08:00
c7cca11ad1
update NAC3
2021-11-11 16:32:37 +08:00
a8129093df
artiq_run: port to NAC3 (WIP)
2021-11-10 21:31:03 +08:00
df87cc88d6
coredevice/ad9912: port to NAC3
2021-11-10 21:27:06 +08:00
93f24c9f94
coredevice/urukul: port to NAC3
2021-11-10 19:01:44 +08:00
31955d0c7a
coredevice/spi2: port to NAC3
2021-11-10 17:23:44 +08:00
b7313ddc32
coredevice/rtio: fix tuple annotation
2021-11-10 15:32:07 +08:00
262cd62544
examples/blink_forever: port to NAC3
2021-11-10 13:59:59 +08:00
2f031285a4
coredevice/ttl: port to NAC3
2021-11-10 13:58:54 +08:00
deb8a77464
coredevice/rtio: port to NAC3
2021-11-10 13:57:03 +08:00
8f596ed04f
coredevice: fix typing problems
2021-11-10 12:37:05 +08:00
c8ebd80fe2
NAC3 integration WIP
2021-11-10 12:18:20 +08:00
db3e5e83e6
bump misoc
2021-11-08 16:59:08 +08:00
09945ecc4d
gateware: fix drtio/dma tests
2021-11-08 16:59:08 +08:00
02119282b8
build_soc: build VexRiscv_G if not kasli v1.x
2021-11-08 16:59:08 +08:00
750b0ce46d
ddb_temp: select appropriate compiler target
2021-11-08 16:59:08 +08:00
531670d6c5
dyld: check ABI
2021-11-08 16:59:08 +08:00
0f660735bf
ll_gen: adjust csr address by detecting target class
2021-11-08 16:59:08 +08:00
0755757601
compiler/tb: use FPU
2021-11-08 16:59:08 +08:00
0d708cd61a
compiler/target: split RISCV target into float/non-float
2021-11-08 16:59:08 +08:00
03b803e764
firmware: adjust csr separation
2021-11-08 16:59:08 +08:00
b3e315e24a
rust: find json file using CARGO_TRIPLE
2021-11-08 16:59:08 +08:00
0898e101e2
board_misoc: reuse riscv dir for comm & kernel
2021-11-08 16:59:08 +08:00
cb247f235f
gateware: pass adr_w/data_w to submodules
2021-11-08 16:59:08 +08:00
90f944481c
kernel_cpu: add fpu if not kasli v1.x
2021-11-08 16:59:08 +08:00
d84ad0095b
comm_cpu: select 64b bus if not kasli v1.x
2021-11-08 16:59:08 +08:00
dd68b4ab82
mailbox: parametrize address width
2021-11-08 16:59:08 +08:00
c6e0e26440
drtio: accept 32b/64b bus
2021-11-08 16:59:08 +08:00
8da924ec0f
dma: set conversion granularity using bus width
2021-11-08 16:59:08 +08:00
e5620a6b7f
language: remove old type annotations
2021-11-03 22:07:44 +08:00
977543e05a
Merge branch 'master' into nac3
2021-11-03 21:37:18 +08:00
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
...
Fastino cic
2021-10-28 17:44:20 +02:00
5a5b0cc7c0
fastino: expand docs
2021-10-28 15:19:48 +00:00
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings ( #1773 )
2021-10-28 16:34:22 +08:00
9b1d7e297d
runtime: clock input specification improvements
...
closes #1735
2021-10-28 16:21:51 +08:00
1ff474893d
Revert "fastino: make driver filter order configurable"
...
This reverts commit 10c37b87ec
2021-10-28 06:29:56 +00:00
10c37b87ec
fastino: make driver filter order configurable
2021-10-27 20:24:58 +00:00
c940f104f1
artiq_flash: fix gateware header not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
0aa8a739aa
sayma_rtm: fix RTM firmware not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
d5fa3d131a
cargo.lock: update libc version for libfringe
2021-10-16 17:42:24 +08:00
6d3164a912
riscv: print mtval on panic
2021-10-16 17:42:24 +08:00
46326716fd
runtime: bump libfringe, impl ecall abi
...
See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
0a59c889de
satman/kern: init locked PMP on startup
2021-10-16 17:42:24 +08:00
27a7a96626
runtime: setup pmp + transfer to user
2021-10-16 17:42:24 +08:00
a0bf11b465
riscv: impl pmp
2021-10-16 17:42:24 +08:00
790a20edf6
linker: generate stack guard + symbol
2021-10-16 17:42:24 +08:00
fanmingyu212
178a86bcda
master: add an argument to set an experiment subdirectory
...
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
2021-10-15 16:54:31 +08:00
fbd5c70250
Revert "runtime: expose rint from libm"
...
Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:58 +08:00
35d21c98d3
Revert "runtime: expose rint from libm"
...
Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:04 +08:00
17c283d091
runtime: expose rint from libm
2021-10-10 20:40:56 +08:00
f5100702f6
runtime: expose rint from libm
2021-10-10 20:40:17 +08:00
3c1cbf47d2
phaser: add more slack during init. Closes #1757
2021-10-10 16:18:55 +08:00
3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
97909d7619
remove old compiler, add nac3 dependency (WIP)
2021-10-08 00:30:27 +08:00
59065c4663
alloc_list: support alloc w/ large align
...
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-10-07 12:38:03 +08:00
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
a8333053c9
sinara_tester: add device_db and test selection CLI options
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-27 17:44:50 +08:00
3ed10221d8
compiler: remove big-endian support. Closes #1590
2021-09-13 13:40:24 +08:00
e8a7a8f41e
compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found
2021-09-13 10:40:54 +08:00
ffb1e3ec2d
wavesynth: np.int is deprecated
2021-09-13 07:02:35 +08:00
2d79d824f9
firmware: remove minor or1k leftovers
2021-09-12 20:03:37 +08:00
a573dcf3f9
board_misoc/build: use rv32 as target arg
...
The original rv64 argument was only to match the misoc counterpart.
2021-09-10 14:11:23 +08:00
448974fe11
runtime/main: cleanup
2021-09-10 13:59:53 +08:00
b091d8cb66
kernel: flush cache before mod_init
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This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
2021-09-10 13:25:12 +08:00
5394d04669
test_spi: add delay
2021-09-10 13:25:12 +08:00
b8ed5a0d91
alloc: fix alignment for riscv32 arch
2021-09-10 13:25:12 +08:00
2213e7ffac
ksupp/rtio/exception: fix timestamp
2021-09-10 13:25:12 +08:00
09ffd9de1e
dma: fix timestamp fetch
2021-09-10 13:25:12 +08:00
051a14abf2
rtio/dma: fix endianness
2021-09-10 13:25:12 +08:00
c6ba0f3cf4
ksupport: fix dma cslice (ffi)
2021-09-10 13:25:12 +08:00
c812a837ab
runtime: enlarge stack size
2021-09-10 13:25:12 +08:00
a596db404d
satman: fix cargo xbuild sysroot
2021-09-10 13:25:12 +08:00
4fab267593
cargo: std dependency hack
2021-09-10 13:25:12 +08:00
dcbd9f905c
cargo: use cargo xbuild
2021-09-10 13:25:12 +08:00
9f6b3f6014
firmware: clarify target triple
...
The lack of compressed instruction support can be inferred from the target triple, literally.
2021-09-10 13:25:12 +08:00
4619a33db4
test: remove broken array return tests
...
Removed test cases that do not respect lifetime/scope constraint.
See discussion in artiq-zynq repo: M-Labs/artiq-zynq#119
Referred to the patch from @dnadlinger. 5faa30a837
2021-09-10 13:25:12 +08:00
5985f7efb5
syscall: lower nowrite to inaccessiblememonly
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In the origin implementation, the `nowrite` flag literally means not writing memory at all.
Due to the usage of flags on certain functions, it results in the same issues found in artiq-zynq after optimization passes. (M-Labs/artiq-zynq#119 )
A fix wrote by @dnadlinger can resolve this issue. (c1e46cc7c8
2021-09-10 13:25:12 +08:00
6db7280b09
flake: board package WIP
2021-09-10 13:25:12 +08:00
d8ac429059
dyld: streamline lib.rs
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Only riscv32 is supported anyway, no need to have excessive architecture check.
2021-09-10 13:25:12 +08:00
798774192d
slave_fpga/bootloader: read in little endian
2021-09-10 13:25:12 +08:00
eecd825d23
firmware: suppress warning
2021-09-10 13:25:12 +08:00
1da0554a49
pcr: purge
2021-09-10 13:25:12 +08:00
5d0a8cf9ac
llvm_ir_gen: fix indent
2021-09-10 13:25:12 +08:00
70507e1b72
Cargo.lock: update
2021-09-10 13:25:12 +08:00
c113cd6bf5
libfringe: bump
2021-09-10 13:25:12 +08:00
61b0170a12
firmware: purge or1k
2021-09-10 13:25:12 +08:00
af263ffe1f
ksupport: fix rpc, cache signature (FFI)
...
The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
2021-09-10 13:25:12 +08:00
a833974b50
analyzer: fix endianness
2021-09-10 13:25:12 +08:00
d623acc29d
llvm_ir_gen: fix now with now_pinning & little-endian target
2021-09-10 13:25:12 +08:00
8fa47b8119
rpc: enforce alignment
2021-09-10 13:25:12 +08:00
de0f2d4a28
firmware: adopt endianness protocol in artiq-zynq
...
Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
2021-09-10 13:25:12 +08:00
9afe63c08a
ksupport: fix proto_artiq dependency
2021-09-10 13:25:12 +08:00
29a2f106d1
ksupport: replace asm with llvm_asm
2021-09-10 13:25:12 +08:00
b30ed75e69
kernel.ld: load elf header and prog headers
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ld.lld has a habit of not putting the headers under any load sections.
However, the headers are needed by libunwind to handle exception raised by the kernel.
Creating PT_LOAD section with FILEHDR and PHDRS solves this issue. Other PHDRS are also specified as linkers (not limited to ld.lld) will not create additional unspecified headers even when necessary.
2021-09-10 13:25:12 +08:00
279593f984
ksupport.ld: merge sbss with bss
2021-09-10 13:25:12 +08:00
1ba8c8dfee
runtime: remove irq again
2021-09-10 13:25:12 +08:00
3d629006df
makefiles: revert byte-swaps
2021-09-10 13:25:12 +08:00
7542105f0f
board_misoc: remove pcr
...
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
2021-09-10 13:25:12 +08:00
01ca114c66
runtime: remove irq dependency
2021-09-10 13:25:12 +08:00
36171f2c61
runtime: remove inaccurate sp on panic
2021-09-10 13:25:12 +08:00
01e357e5d3
ksupport.ld: reduce load section alignment
2021-09-10 13:25:12 +08:00
f77b607b56
compiler: generate symbols
2021-09-10 13:25:12 +08:00
1293e0750e
ld, makefiles: use ld.lld
2021-09-10 13:25:12 +08:00
fc42d053d9
kernel: use vexriscv
2021-09-10 13:25:12 +08:00
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
e8fe8409b2
libartiq_support: compatibility with recent stable rustc
2021-09-10 13:25:12 +08:00
cabe5ace8e
compiler: remove DebugInfoEmitter for now
...
Causes problems with LLVM 9 and not needed at first.
2021-09-10 13:25:12 +08:00
6629a49e86
compiler: use LLVM binutils/linker for Arm as well
...
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
2021-09-10 13:25:12 +08:00
43d120359d
compiler: switch to upstream llvmlite and RISC-V target
2021-09-10 13:25:12 +08:00
5656e52581
remove profiler
2021-09-10 13:25:12 +08:00
1b8b4baf6a
ksupport: fix panic, libc, unwind
2021-09-10 13:25:12 +08:00
905330b0f1
ksupport: handle riscv exceptions
2021-09-10 13:25:12 +08:00
50a62b3d42
liballoc: change align to 16 bytes
2021-09-10 13:25:12 +08:00
7f0bc9f7f0
runtime/makefile: specify emulation, flip endianness
2021-09-10 13:25:12 +08:00
c42adfe6fd
runtime.ld: merge .sbss & .bss
2021-09-10 13:25:12 +08:00
f56152e72f
rust: fix dependencies
2021-09-10 13:25:12 +08:00
c800b6c8d3
runtime: update rust alloc, managed
2021-09-10 13:25:09 +08:00
e99061b013
runtime: add riscv
2021-09-10 13:23:22 +08:00
ecedec577c
runtime: impl riscv exception handling
2021-09-10 13:23:15 +08:00
252594a606
runtime: impl riscv panic handler
2021-09-10 13:20:31 +08:00
31bf17563c
personality: update from rust/panic_unwind
2021-09-10 13:20:31 +08:00
bfddd8a30f
libdyld: add riscv support
2021-09-10 13:20:31 +08:00
ad3037d0f6
libc: add minimal C types
2021-09-10 13:20:31 +08:00
daaf6c3401
libunwind: add rust interface
2021-09-10 13:20:31 +08:00
6d9cebfd42
satman: handle .sbss generation
2021-09-10 13:20:31 +08:00
96438c9da7
satman: make fbi big-endian
2021-09-10 13:20:31 +08:00
6535b2f089
satman: fix feature
2021-09-10 13:20:31 +08:00
45adaa1d98
satman: add riscv exception handling
2021-09-10 13:20:31 +08:00
869a282410
satman: use riscv
2021-09-10 13:20:31 +08:00
ebb9f298b5
proto_artiq: update alloc type path
2021-09-10 13:20:31 +08:00
97a0132f15
libio: update alloc type path
2021-09-10 13:20:31 +08:00
37ea863004
libio: pin failure version
2021-09-10 13:20:31 +08:00
3ff74e0693
bootloader: handle .sbss generation in .ld
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
448fe0e8cf
bootloader: fix panic
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
8294d7fea5
bootloader: swap endianness
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
13032272fd
bootloader: add rv32 exception handler
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
46102ee737
board_misoc: build vectors.S with rv64 target in misoc
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
b87ea79d51
rv32: rm irq & vexriscv-rust
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
9aee42f0f2
rv32/boot: remove hotswap
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
82b4052cd6
libboard_misoc: vexriscv integration
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Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
Leon Riesebos
2cf144a60c
ddb_template: edge counter keys correspond with according ttl keys
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previously ttl_counter_0 and ttl_0 could be on completely different physical ttl output channels
with this change, ttl_0_counter (note the changed key format) is always on the same channel as ttl_0
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
2021-09-06 09:06:04 +08:00
4d7bd3ee32
phaser: fail init() if frame timestamp measurement times out
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-03 12:01:26 +02:00
075cb26dd7
phaser: rename get_next_frame_timestamp() to get_next_frame_mu()
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and implement review comments (PR #1749 )
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-03 09:58:01 +02:00
7aebf02f84
phaser: docs: add reference to get_next_frame_timestamps(), fix typo
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-01 17:44:46 +02:00
61b44d40dd
phaser: add labels to debug init prints
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-01 17:43:30 +02:00
65f8a97b56
phaser: add helpers to align updates to the RTIO timeline
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-01 17:42:54 +02:00
SingularitySurfer
65f63e6927
fix suservo start
2021-08-19 07:38:48 +00:00
a53162d01d
tester: tweak suservo
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* p gain 1 to get reasonable power
* refine testing instructions and comments
2021-08-19 09:17:14 +02:00
SingularitySurfer
4d21a72407
Implement SUServo tester.
2021-08-18 15:10:27 +00:00
Mikołaj Sowiński
898122f3e5
Added support for HVAMP_8CH ( #1741 )
2021-08-16 13:39:00 +08:00
420891ba54
syntax
2021-08-12 13:01:35 +08:00
9f94bc61ae
missing part of 477b1516d
2021-08-12 12:55:37 +08:00
c69a1316ad
compiler: stop using sys.version_info for parser
2021-08-12 12:52:24 +08:00
477b1516d3
remove profiler
2021-08-12 12:51:55 +08:00
67847f98f4
artiq_run: fix multiarch
2021-08-12 12:48:10 +08:00
7879d3630b
made kc705/gtx interface more similar to kasli/gtp
2021-08-10 18:53:52 +08:00
242dfae38e
kc705: fix DRTIO targets
2021-08-06 15:41:47 +08:00
5111132ef0
ICAP: prevent sayma from using it ( #1740 )
2021-08-06 15:08:30 +08:00
dc546630e4
kc705: DRTIO variants WIP
2021-08-06 14:41:41 +08:00
fd824f7ad0
ddb_template: print LED channel nos on Kasli v2
2021-08-05 17:29:38 +02:00
c9608c0a89
zotino: default div_read unified with ad53xx at 16, fix ad53xx doc
2021-08-05 17:42:11 +08:00
6b88ea563d
talk to ICAP primitive to restart gateware ( #1733 )
2021-08-05 17:00:31 +08:00
97e994700b
compiler: turn __repr__ into __str__ when sphinx is used. Closes #741
2021-08-05 11:32:20 +08:00
c3d765f745
ad9910: fix type annotations
2021-08-05 11:30:54 +08:00
53a98acfe4
artiq_flash: cleanup openocd handling, do not follow symlinks
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Not following symlinks allows files to be added to OpenOCD via nixpkgs buildEnv.
2021-07-26 17:01:24 +08:00
30e5e06a33
moninj: fix read of incomplete data ( #1729 )
2021-07-22 17:56:38 +08:00
ebb67eaeee
applets: add length warning message on plot for plot_xy_hist and fix bug ( #1725 )
2021-07-19 15:45:48 +08:00
943a95e07a
applets: add data length warning message for plot_xy ( #1722 )
2021-07-19 15:14:15 +08:00
e996b5f635
applets: fix warning timing
2021-07-19 12:26:01 +08:00
4fb8ea5b73
artiq_flash: determine which firmware to flash by looking at filesystem
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Closes #1719
2021-07-14 16:43:00 +08:00
5cd721c514
applets: add plot_hist dataset length mismatch warning ( #1718 )
2021-07-14 15:57:55 +08:00
Star Chen
6ce9c26402
GUI: add option to create new datasets ( #1716 )
2021-07-13 12:53:35 +08:00
2204fd2b22
adf5356: add delay to sync()
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Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-07-08 10:03:20 +08:00
b10d1bdd37
compiler: proper union find
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The find implementation was not very optimized, and the unify function
did not consider tree height and may build some tall trees.
2021-07-07 09:22:16 +08:00
4ede58e44b
compiler: reduce calls to TypedTreeHasher
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We need to check if our inference reached a fixed point. This is checked
using hash of the types in the AST, which is very slow. This patch
avoids computing the hash if we can make sure that the AST is definitely
changed, which is when we parse a new function.
For some simple programs with many functions, this can significantly
reduce the compile time by up to ~30%.
2021-07-07 09:22:16 +08:00
822e8565f7
compiler: supports kernel decorators with path
2021-07-02 17:01:31 +08:00
6fb31a7abb
compiler: allow empty list in quote
2021-07-02 15:16:19 +08:00
0806b67dbf
compiler: speedup list processing
2021-07-02 14:22:25 +08:00
f531af510c
compiler: fixed embedding annotation evaluation
2021-06-25 11:32:23 +08:00
c29a149d16
compiler: allows string annotation
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According to PEP484, type hint can be a string literal for forward
references. With PEP563, type hint would be preserved in annotations in
string form.
2021-06-25 11:01:48 +08:00
Etienne Wodey
68268e3db8
docs: fix some formatting issues
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-23 20:29:43 +08:00
Etienne Wodey
cca654bd47
test_device_db: fix on Windows (tempfile access limitations)
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-21 16:47:22 +08:00
Etienne Wodey
8bedf278f0
set_dataset: pass HDF5 options as a dict, not as loose kwargs
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-17 16:43:05 +02:00
Etienne Wodey
12ef907f34
master/databases: fix AttributeError in DatasetDB.set()
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Add corresponding unit test.
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-17 16:30:38 +02:00
Etienne Wodey
d8b1e59538
datasets: allow passing options to HDF5 backend (e.g. compression)
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This breaks the internal dataset representation used by applets
and when saving to disk (``dataset_db.pyon``).
See ``test/test_dataset_db.py`` and ``test/test_datasets.py``
for examples.
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-17 12:04:16 +02:00
Etienne Wodey
b8ab5f2607
master/databases: use tools.file_import to load the device_db
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Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-17 07:58:17 +08:00
