mirror of https://github.com/m-labs/artiq.git
fastino: make driver filter order configurable
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@ -39,13 +39,15 @@ class Fastino:
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:param core_device: Core device name (default: "core")
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:param log2_width: Width of DAC channel group (logarithm base 2).
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Value must match the corresponding value in the RTIO PHY (gateware).
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:param order: CIC filter interpolation order.
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"""
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kernel_invariants = {"core", "channel", "width"}
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kernel_invariants = {"core", "channel", "width", "order"}
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def __init__(self, dmgr, channel, core_device="core", log2_width=0):
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def __init__(self, dmgr, channel, core_device="core", log2_width=0, order=3):
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self.channel = channel << 8
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self.core = dmgr.get(core_device)
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self.width = 1 << log2_width
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self.order = order
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@kernel
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def init(self):
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@ -222,8 +224,7 @@ class Fastino:
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Returns the actual interpolation rate.
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The actual overall interpolation gain including gain compensation is
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`actual_rate**order/2**ceil(log2(actual_rate**order))`
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where `order = 3`.
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`actual_rate**order/2**ceil(log2(actual_rate**order))`.
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"""
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if rate <= 0 or rate > 1 << 16:
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raise ValueError("rate out of bounds")
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@ -232,15 +233,14 @@ class Fastino:
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while rate_mantissa > 1 << 6:
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rate_exponent += 1
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rate_mantissa >>= 1
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order = 3
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gain = 1
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for i in range(order):
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for i in range(self.order):
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gain *= rate_mantissa
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gain_exponent = 0
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while gain > 1 << gain_exponent:
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gain_exponent += 1
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gain_exponent += order*rate_exponent
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assert gain_exponent <= order*16
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gain_exponent += self.order*rate_exponent
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assert gain_exponent <= self.order*16
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self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
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return rate_mantissa << rate_exponent
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@ -252,6 +252,6 @@ class Fastino:
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continous DAC updates enabled (see :meth:`set_continuous`).
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This resets and settles the interpolators. There will be no output
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updates for the next `order = 3` input samples.
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updates for the next `order` input samples.
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"""
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self.write(0x27, channel_mask)
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