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runtime: add riscv
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@ -28,6 +28,7 @@ logger_artiq = { path = "../liblogger_artiq" }
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board_artiq = { path = "../libboard_artiq" }
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proto_artiq = { path = "../libproto_artiq", features = ["log", "alloc"] }
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smoltcp = { version = "0.6.0", default-features = false, features = ["rust-1_28", "alloc", "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"] }
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riscv = { version = "0.6.0", features = ["inline-asm"] }
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[dependencies.fringe]
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git = "https://github.com/m-labs/libfringe"
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@ -25,6 +25,7 @@ extern crate board_misoc;
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extern crate board_artiq;
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extern crate logger_artiq;
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extern crate proto_artiq;
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extern crate riscv;
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use core::cell::RefCell;
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use core::convert::TryFrom;
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@ -41,6 +42,8 @@ use proto_artiq::{mgmt_proto, moninj_proto, rpc_proto, session_proto, kernel_pro
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#[cfg(has_rtio_analyzer)]
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use proto_artiq::analyzer_proto;
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use riscv::register::{mcause, mepc};
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mod rtio_clocking;
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mod rtio_mgt;
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