M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-24 10:54:02 +08:00
Code Issues Projects Releases Wiki Activity

suservo: use default urukul profile

Browse Source
This commit is contained in:
occheung 2022-01-06 16:15:51 +08:00 committed by Sébastien Bourdeauducq
parent 8b45f917d1
commit cea0a15e1e
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/gateware/suservo/dds_ser.py
View File

@ -2,6 +2,8 @@ import logging
from migen import *
from artiq.coredevice.urukul import DEFAULT_PROFILE
from . import spi
@ -26,7 +28,8 @@ class DDS(spi.SPISimple):
self.profile = [Signal(32 + 16 + 16, reset_less=True)
for i in range(params.channels)]
cmd = Signal(8, reset=0x15) # write to single tone profile 7
# write to single tone default profile
cmd = Signal(8, reset=0x0e + DEFAULT_PROFILE)
assert params.width == len(cmd) + len(self.profile[0])
self.sync += [