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phaser: fail init() if frame timestamp measurement times out
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
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@ -18,7 +18,7 @@ Highlights:
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- Improved documentation
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- Expose the DAC coarse mixer and ``sif_sync``
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- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
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- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_timestamp()``)
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- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``)
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* New hardware support:
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
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@ -2,7 +2,6 @@ from numpy import int32, int64
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from artiq.language.core import kernel, delay_mu, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data, rtio_input_timestamp
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from artiq.coredevice.core import rtio_get_counter
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from artiq.language.units import us, ns, ms, MHz
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from artiq.language.types import TInt32
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from artiq.coredevice.dac34h84 import DAC34H84
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@ -202,6 +201,8 @@ class Phaser:
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# determine the origin for frame-aligned timestamps
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self.measure_frame_timestamp()
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if self.frame_tstamp < 0:
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raise ValueError("frame timestamp measurement timed out")
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# reset
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self.set_cfg(dac_resetb=0, dac_sleep=1, dac_txena=0,
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@ -482,7 +483,7 @@ class Phaser:
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See `get_next_frame_mu()`.
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"""
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rtio_output(self.channel_base << 8, 0) # read any register
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self.frame_tstamp = rtio_input_timestamp(rtio_get_counter() + 125_000, self.channel_base)
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self.frame_tstamp = rtio_input_timestamp(now_mu() + 4 * self.t_frame, self.channel_base)
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delay(100 * us)
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@kernel
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