mirror of https://github.com/m-labs/artiq.git
coredevice/urukul: port to NAC3
This commit is contained in:
parent
31955d0c7a
commit
93f24c9f94
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@ -1,15 +1,17 @@
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from numpy import int32, int64
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from artiq.language.core import kernel, delay, portable, at_mu, now_mu
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from artiq.language.core import nac3, KernelInvariant, kernel, portable
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from artiq.language.units import us, ms
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from artiq.language.types import TInt32, TFloat, TBool
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice.core import Core
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from artiq.coredevice.spi2 import *
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from artiq.coredevice.ttl import TTLOut
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SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
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0 * spi.SPI_INPUT | 1 * spi.SPI_CS_POLARITY |
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0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
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0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
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SPI_CONFIG = (0 * SPI_OFFLINE | 0 * SPI_END |
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0 * SPI_INPUT | 1 * SPI_CS_POLARITY |
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0 * SPI_CLK_POLARITY | 0 * SPI_CLK_PHASE |
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0 * SPI_LSB_FIRST | 0 * SPI_HALF_DUPLEX)
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# SPI clock write and read dividers
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SPIT_CFG_WR = 2
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@ -54,8 +56,8 @@ CS_DDS_CH3 = 7
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@portable
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def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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clk_sel, sync_sel, rst, io_rst, clk_div):
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def urukul_cfg(rf_sw: int32, led: int32, profile: int32, io_update: int32, mask_nu: int32,
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clk_sel: int32, sync_sel: int32, rst: int32, io_rst: int32, clk_div: int32) -> int32:
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"""Build Urukul CPLD configuration register"""
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return ((rf_sw << CFG_RF_SW) |
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(led << CFG_LED) |
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@ -71,56 +73,45 @@ def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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@portable
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def urukul_sta_rf_sw(sta):
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def urukul_sta_rf_sw(sta: int32) -> int32:
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"""Return the RF switch status from Urukul status register value."""
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return (sta >> STA_RF_SW) & 0xf
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@portable
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def urukul_sta_smp_err(sta):
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def urukul_sta_smp_err(sta: int32) -> int32:
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"""Return the SMP_ERR status from Urukul status register value."""
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return (sta >> STA_SMP_ERR) & 0xf
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@portable
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def urukul_sta_pll_lock(sta):
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def urukul_sta_pll_lock(sta: int32) -> int32:
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"""Return the PLL_LOCK status from Urukul status register value."""
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return (sta >> STA_PLL_LOCK) & 0xf
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@portable
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def urukul_sta_ifc_mode(sta):
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def urukul_sta_ifc_mode(sta: int32) -> int32:
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"""Return the IFC_MODE status from Urukul status register value."""
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return (sta >> STA_IFC_MODE) & 0xf
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@portable
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def urukul_sta_proto_rev(sta):
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def urukul_sta_proto_rev(sta: int32) -> int32:
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"""Return the PROTO_REV value from Urukul status register value."""
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return (sta >> STA_PROTO_REV) & 0x7f
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class _RegIOUpdate:
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def __init__(self, cpld):
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self.cpld = cpld
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@kernel
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def pulse(self, t: TFloat):
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cfg = self.cpld.cfg_reg
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self.cpld.cfg_write(cfg | (1 << CFG_IO_UPDATE))
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delay(t)
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self.cpld.cfg_write(cfg)
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@nac3
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class _DummySync:
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def __init__(self, cpld):
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self.cpld = cpld
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@kernel
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def set_mu(self, ftw: TInt32):
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def set_mu(self, ftw: int32):
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pass
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@nac3
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class CPLD:
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"""Urukul CPLD SPI router and configuration interface.
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@ -159,7 +150,16 @@ class CPLD:
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front panel SMA with no clock connected), then the ``init()`` method of
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the DDS channels can fail with the error message ``PLL lock timeout``.
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"""
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kernel_invariants = {"refclk", "bus", "core", "io_update", "clk_div"}
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core: KernelInvariant[Core]
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refclk: KernelInvariant[float]
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bus: KernelInvariant[SPIMaster]
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io_update: KernelInvariant[TTLOut]
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clk_div: KernelInvariant[int32]
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sync: KernelInvariant[_DummySync]
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cfg_reg: int32
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att_reg: int32
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sync_div: int32
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def __init__(self, dmgr, spi_device, io_update_device=None,
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dds_reset_device=None, sync_device=None,
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@ -176,13 +176,17 @@ class CPLD:
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if io_update_device is not None:
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self.io_update = dmgr.get(io_update_device)
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else:
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self.io_update = _RegIOUpdate(self)
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self.io_update = _RegIOUpdate(self.core, self)
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# NAC3TODO
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raise NotImplementedError
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if dds_reset_device is not None:
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self.dds_reset = dmgr.get(dds_reset_device)
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if sync_device is not None:
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self.sync = dmgr.get(sync_device)
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if sync_div is None:
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sync_div = 2
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# NAC3TODO
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raise NotImplementedError
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else:
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self.sync = _DummySync(self)
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assert sync_div is None
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@ -196,7 +200,7 @@ class CPLD:
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self.sync_div = sync_div
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@kernel
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def cfg_write(self, cfg: TInt32):
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def cfg_write(self, cfg: int32):
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"""Write to the configuration register.
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See :func:`urukul_cfg` for possible flags.
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@ -204,13 +208,13 @@ class CPLD:
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:param cfg: 24 bit data to be written. Will be stored at
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:attr:`cfg_reg`.
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 24,
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 24,
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SPIT_CFG_WR, CS_CFG)
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self.bus.write(cfg << 8)
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self.cfg_reg = cfg
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@kernel
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def sta_read(self) -> TInt32:
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def sta_read(self) -> int32:
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"""Read the status register.
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Use any of the following functions to extract values:
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@ -223,13 +227,13 @@ class CPLD:
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:return: The status register value.
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 24,
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self.bus.set_config_mu(SPI_CONFIG | SPI_END | SPI_INPUT, 24,
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SPIT_CFG_RD, CS_CFG)
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self.bus.write(self.cfg_reg << 8)
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return self.bus.read()
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@kernel
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def init(self, blind: TBool = False):
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def init(self, blind: bool = False):
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"""Initialize and detect Urukul.
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Resets the DDS I/O interface and verifies correct CPLD gateware
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@ -246,13 +250,14 @@ class CPLD:
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else:
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proto_rev = urukul_sta_proto_rev(self.sta_read())
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if proto_rev != STA_PROTO_REV_MATCH:
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raise ValueError("Urukul proto_rev mismatch")
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delay(100 * us) # reset, slack
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# NAC3TODO raise ValueError("Urukul proto_rev mismatch")
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pass
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self.core.delay(100. * us) # reset, slack
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self.cfg_write(cfg)
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if self.sync_div:
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at_mu(now_mu() & ~0xf) # align to RTIO/2
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if self.sync_div != 0:
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at_mu(now_mu() & ~int64(0xf)) # align to RTIO/2
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self.set_sync_div(self.sync_div) # 125 MHz/2 = 1 GHz/16
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delay(1 * ms) # DDS wake up
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self.core.delay(1. * ms) # DDS wake up
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@kernel
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def io_rst(self):
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@ -260,8 +265,8 @@ class CPLD:
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self.cfg_write(self.cfg_reg | (1 << CFG_IO_RST))
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self.cfg_write(self.cfg_reg & ~(1 << CFG_IO_RST))
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@kernel
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def cfg_sw(self, channel: TInt32, on: TBool):
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# NAC3TODO @kernel
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def cfg_sw(self, channel: int32, on: bool):
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"""Configure the RF switches through the configuration register.
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These values are logically OR-ed with the LVDS lines on EEM1.
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@ -277,15 +282,15 @@ class CPLD:
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self.cfg_write(c)
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@kernel
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def cfg_switches(self, state: TInt32):
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def cfg_switches(self, state: int32):
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"""Configure all four RF switches through the configuration register.
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:param state: RF switch state as a 4 bit integer.
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"""
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self.cfg_write((self.cfg_reg & ~0xf) | state)
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@portable(flags={"fast-math"})
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def mu_to_att(self, att_mu: TInt32) -> TFloat:
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@portable
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def mu_to_att(self, att_mu: int32) -> float:
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"""Convert a digital attenuation setting to dB.
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:param att_mu: Digital attenuation setting.
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@ -293,20 +298,21 @@ class CPLD:
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"""
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return (255 - (att_mu & 0xff)) / 8
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@portable(flags={"fast-math"})
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def att_to_mu(self, att: TFloat) -> TInt32:
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@portable
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def att_to_mu(self, att: float) -> int32:
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"""Convert an attenuation setting in dB to machine units.
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:param att: Attenuation setting in dB.
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:return: Digital attenuation setting.
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"""
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code = int32(255) - int32(round(att * 8))
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code = 255 - round(att * 8.)
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if code < 0 or code > 255:
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raise ValueError("Invalid urukul.CPLD attenuation!")
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# NAC3TODO raise ValueError("Invalid urukul.CPLD attenuation!")
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pass
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return code
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@kernel
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def set_att_mu(self, channel: TInt32, att: TInt32):
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# NAC3TODO @kernel
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def set_att_mu(self, channel: int32, att: int32):
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"""Set digital step attenuator in machine units.
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This method will also write the attenuator settings of the three
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@ -322,20 +328,20 @@ class CPLD:
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self.set_all_att_mu(a)
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@kernel
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def set_all_att_mu(self, att_reg: TInt32):
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def set_all_att_mu(self, att_reg: int32):
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"""Set all four digital step attenuators (in machine units).
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.. seealso:: :meth:`set_att_mu`
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:param att_reg: Attenuator setting string (32 bit)
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32,
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
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SPIT_ATT_WR, CS_ATT)
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self.bus.write(att_reg)
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self.att_reg = att_reg
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@kernel
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def set_att(self, channel: TInt32, att: TFloat):
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# NAC3TODO @kernel
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def set_att(self, channel: int32, att: float):
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"""Set digital step attenuator in SI units.
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This method will write the attenuator settings of all four channels.
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@ -350,7 +356,7 @@ class CPLD:
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self.set_att_mu(channel, self.att_to_mu(att))
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@kernel
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def get_att_mu(self) -> TInt32:
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def get_att_mu(self) -> int32:
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"""Return the digital step attenuator settings in machine units.
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The result is stored and will be used in future calls of
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@ -360,18 +366,18 @@ class CPLD:
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:return: 32 bit attenuator settings
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT, 32,
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self.bus.set_config_mu(SPI_CONFIG | SPI_INPUT, 32,
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SPIT_ATT_RD, CS_ATT)
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self.bus.write(0) # shift in zeros, shift out current value
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32,
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
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SPIT_ATT_WR, CS_ATT)
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delay(10 * us)
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self.core.delay(10. * us)
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self.att_reg = self.bus.read()
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self.bus.write(self.att_reg) # shift in current value again and latch
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return self.att_reg
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@kernel
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def get_channel_att_mu(self, channel: TInt32) -> TInt32:
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def get_channel_att_mu(self, channel: int32) -> int32:
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"""Get digital step attenuator value for a channel in machine units.
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The result is stored and will be used in future calls of
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@ -386,7 +392,7 @@ class CPLD:
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return int32((self.get_att_mu() >> (channel * 8)) & 0xff)
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@kernel
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def get_channel_att(self, channel: TInt32) -> TFloat:
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def get_channel_att(self, channel: int32) -> float:
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"""Get digital step attenuator value for a channel in SI units.
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.. seealso:: :meth:`get_channel_att_mu`
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@ -399,7 +405,7 @@ class CPLD:
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return self.mu_to_att(self.get_channel_att_mu(channel))
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@kernel
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def set_sync_div(self, div: TInt32):
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def set_sync_div(self, div: int32):
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"""Set the SYNC_IN AD9910 pulse generator frequency
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and align it to the current RTIO timestamp.
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@ -412,11 +418,11 @@ class CPLD:
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"""
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ftw_max = 1 << 4
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ftw = ftw_max // div
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assert ftw * div == ftw_max
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# NAC3TODO assert ftw * div == ftw_max
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self.sync.set_mu(ftw)
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@kernel
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def set_profile(self, profile: TInt32):
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# NAC3TODO @kernel
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def set_profile(self, profile: int32):
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"""Set the PROFILE pins.
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The PROFILE pins are common to all four DDS channels.
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@ -426,3 +432,18 @@ class CPLD:
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cfg = self.cfg_reg & ~(7 << CFG_PROFILE)
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cfg |= (profile & 7) << CFG_PROFILE
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self.cfg_write(cfg)
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class _RegIOUpdate:
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core: KernelInvariant[Core]
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cpld: KernelInvariant[CPLD]
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def __init__(self, core, cpld):
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self.core = core
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self.cpld = cpld
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@kernel
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def pulse(self, t: float):
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cfg = self.cpld.cfg_reg
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self.cpld.cfg_write(cfg | (1 << CFG_IO_UPDATE))
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delay(t)
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self.cpld.cfg_write(cfg)
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