mirror of https://github.com/m-labs/artiq.git
siphaser: add support for 100mhz rtio
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@ -4,7 +4,7 @@ from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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# This code assumes 125/62.5MHz reference clock and 125MHz or 150MHz RTIO
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# This code assumes 125/62.5MHz reference clock and 100MHz, 125MHz or 150MHz RTIO
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# frequency.
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class SiPhaser7Series(Module, AutoCSR):
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@ -15,9 +15,9 @@ class SiPhaser7Series(Module, AutoCSR):
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self.phase_shift_done = CSRStatus(reset=1)
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self.error = CSR()
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assert rtio_clk_freq in (125e6, 150e6)
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assert rtio_clk_freq in (100e6, 125e6, 150e6)
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# 125MHz/62.5MHz reference clock to 125MHz/150MHz. VCO @ 750MHz.
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# 125MHz/62.5MHz reference clock to 100MHz/125MHz/150MHz. VCO @ 750MHz.
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# Used to provide a startup clock to the transceiver through the Si,
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# we do not use the crystal reference so that the PFD (f3) frequency
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# can be high.
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@ -43,7 +43,7 @@ class SiPhaser7Series(Module, AutoCSR):
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else:
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mmcm_freerun_output = mmcm_freerun_output_raw
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# 125MHz/150MHz to 125MHz/150MHz with controllable phase shift,
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# 100MHz/125MHz/150MHz to 100MHz/125MHz/150MHz with controllable phase shift,
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# VCO @ 1000MHz/1200MHz.
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# Inserted between CDR and output to Si, used to correct
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# non-determinstic skew of Si5324.
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