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zotino: default div_read unified with ad53xx at 16, fix ad53xx doc
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6b88ea563d
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@ -127,9 +127,9 @@ class AD53xx:
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transactions (default: 1)
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:param div_write: SPI clock divider for write operations (default: 4,
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50MHz max SPI clock with {t_high, t_low} >=8ns)
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:param div_read: SPI clock divider for read operations (default: 8, not
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optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO
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valid)
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:param div_read: SPI clock divider for read operations (default: 16, not
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optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO
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valid, and suggests the SPI speed for reads should be <=20 MHz)
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:param vref: DAC reference voltage (default: 5.)
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:param offset_dacs: Initial register value for the two offset DACs, device
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dependent and must be set correctly for correct voltage to mu
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@ -27,15 +27,15 @@ class Zotino(AD53xx):
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:param clr_device: CLR RTIO TTLOut channel name.
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:param div_write: SPI clock divider for write operations (default: 4,
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50MHz max SPI clock)
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:param div_read: SPI clock divider for read operations (default: 8, not
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optimized for speed, but cf data sheet t22: 25ns min SCLK edge to SDO
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valid)
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:param div_read: SPI clock divider for read operations (default: 16, not
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optimized for speed; datasheet says t22: 25ns min SCLK edge to SDO
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valid, and suggests the SPI speed for reads should be <=20 MHz)
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:param vref: DAC reference voltage (default: 5.)
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:param core_device: Core device name (default: "core")
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"""
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def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
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div_write=4, div_read=8, vref=5., core="core"):
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div_write=4, div_read=16, vref=5., core="core"):
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AD53xx.__init__(self, dmgr=dmgr, spi_device=spi_device,
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ldac_device=ldac_device, clr_device=clr_device,
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chip_select=_SPI_CS_DAC, div_write=div_write,
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