mirror of https://github.com/m-labs/artiq.git
coredevice/zotino: port to NAC3
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parent
64877c0588
commit
bd95d9cf3d
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@ -8,17 +8,19 @@ time is an error.
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# Designed from the data sheets and somewhat after the linux kernel
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# iio driver.
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from numpy import int32
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from numpy import int32, int64
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from artiq.language.core import (kernel, portable, delay_mu, delay, now_mu,
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at_mu)
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from artiq.language.core import nac3, kernel, portable, KernelInvariant
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from artiq.language.units import ns, us
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice.core import Core
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from artiq.coredevice.ttl import TTLOut
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from artiq.coredevice.spi2 import *
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SPI_AD53XX_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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SPI_AD53XX_CONFIG = (0*SPI_OFFLINE | 1*SPI_END |
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0*SPI_INPUT | 0*SPI_CS_POLARITY |
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0*SPI_CLK_POLARITY | 1*SPI_CLK_PHASE |
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0*SPI_LSB_FIRST | 0*SPI_HALF_DUPLEX)
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AD53XX_CMD_DATA = 3 << 22
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AD53XX_CMD_OFFSET = 2 << 22
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@ -52,7 +54,7 @@ AD53XX_READ_AB3 = 0x109 << 7
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@portable
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def ad53xx_cmd_write_ch(channel, value, op):
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def ad53xx_cmd_write_ch(channel: int32, value: int32, op: int32) -> int32:
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"""Returns the word that must be written to the DAC to set a DAC
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channel register to a given value.
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@ -67,7 +69,7 @@ def ad53xx_cmd_write_ch(channel, value, op):
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@portable
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def ad53xx_cmd_read_ch(channel, op):
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def ad53xx_cmd_read_ch(channel: int32, op: int32) -> int32:
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"""Returns the word that must be written to the DAC to read a given
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DAC channel register.
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@ -82,7 +84,7 @@ def ad53xx_cmd_read_ch(channel, op):
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# maintain function definition for backward compatibility
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@portable
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def voltage_to_mu(voltage, offset_dacs=0x2000, vref=5.):
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def voltage_to_mu(voltage: float, offset_dacs: int32 = 0x2000, vref: float = 5.) -> int32:
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"""Returns the 16-bit DAC register value required to produce a given output
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voltage, assuming offset and gain errors have been trimmed out.
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@ -100,22 +102,25 @@ def voltage_to_mu(voltage, offset_dacs=0x2000, vref=5.):
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:param vref: DAC reference voltage (default: 5.)
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:return: The 16-bit DAC register value
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"""
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code = int(round((1 << 16) * (voltage / (4. * vref)) + offset_dacs * 0x4))
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code = round(float(1 << 16) * (voltage / (4. * vref))) + offset_dacs * 0x4
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if code < 0x0 or code > 0xffff:
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raise ValueError("Invalid DAC voltage!")
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# NAC3TODO raise ValueError("Invalid DAC voltage!")
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pass
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return code
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@nac3
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class _DummyTTL:
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@portable
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@kernel
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def on(self):
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pass
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@portable
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@kernel
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def off(self):
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pass
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@nac3
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class AD53xx:
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"""Analog devices AD53[67][0123] family of multi-channel Digital to Analog
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Converters.
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@ -137,8 +142,15 @@ class AD53xx:
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experiments. (default: 8192)
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:param core_device: Core device name (default: "core")
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"""
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kernel_invariants = {"bus", "ldac", "clr", "chip_select", "div_write",
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"div_read", "vref", "core"}
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core: KernelInvariant[Core]
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bus: KernelInvariant[SPIMaster]
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ldac: KernelInvariant[TTLOut]
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clr: KernelInvariant[TTLOut]
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chip_select: KernelInvariant[int32]
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div_write: KernelInvariant[int32]
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div_read: KernelInvariant[int32]
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vref: KernelInvariant[float]
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offset_dacs: int32
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def __init__(self, dmgr, spi_device, ldac_device=None, clr_device=None,
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chip_select=1, div_write=4, div_read=16, vref=5.,
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@ -161,7 +173,7 @@ class AD53xx:
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self.core = dmgr.get(core)
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@kernel
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def init(self, blind=False):
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def init(self, blind: bool = False):
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"""Configures the SPI bus, drives LDAC and CLR high, programmes
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the offset DACs, and enables overtemperature shutdown.
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@ -177,22 +189,25 @@ class AD53xx:
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self.chip_select)
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self.write_offset_dacs_mu(self.offset_dacs)
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if not blind:
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ctrl = self.read_reg(channel=0, op=AD53XX_READ_CONTROL)
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ctrl = self.read_reg(0, AD53XX_READ_CONTROL)
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if ctrl == 0xffff:
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raise ValueError("DAC not found")
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if ctrl & 0b10000:
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raise ValueError("DAC over temperature")
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delay(25*us)
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# NAC3TODO raise ValueError("DAC not found")
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pass
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if (ctrl & 0b10000) != 0:
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# NAC3TODO raise ValueError("DAC over temperature")
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pass
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self.core.delay(125.*us) # NAC3TODO try to restore original 25us after kernel invariants
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self.bus.write( # enable power and overtemperature shutdown
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(AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_CONTROL | 0b0010) << 8)
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if not blind:
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ctrl = self.read_reg(channel=0, op=AD53XX_READ_CONTROL)
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ctrl = self.read_reg(0, AD53XX_READ_CONTROL)
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if (ctrl & 0b10111) != 0b00010:
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raise ValueError("DAC CONTROL readback mismatch")
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delay(15*us)
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# NAC3TODO raise ValueError("DAC CONTROL readback mismatch")
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pass
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self.core.delay(115.*us) # NAC3TODO try to restore original 15us after kernel invariants
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@kernel
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def read_reg(self, channel=0, op=AD53XX_READ_X1A):
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def read_reg(self, channel: int32 = 0, op: int32 = AD53XX_READ_X1A) -> int32:
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"""Read a DAC register.
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This method advances the timeline by the duration of two SPI transfers
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@ -205,17 +220,16 @@ class AD53xx:
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:return: The 16 bit register value
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"""
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self.bus.write(ad53xx_cmd_read_ch(channel, op) << 8)
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self.bus.set_config_mu(SPI_AD53XX_CONFIG | spi.SPI_INPUT, 24,
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self.bus.set_config_mu(SPI_AD53XX_CONFIG | SPI_INPUT, 24,
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self.div_read, self.chip_select)
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delay(270*ns) # t_21 min sync high in readback
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self.core.delay(270.*ns) # t_21 min sync high in readback
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self.bus.write((AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_NOP) << 8)
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self.bus.set_config_mu(SPI_AD53XX_CONFIG, 24, self.div_write,
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self.chip_select)
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# FIXME: the int32 should not be needed to resolve unification
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return self.bus.read() & int32(0xffff)
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return self.bus.read() & 0xffff
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@kernel
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def write_offset_dacs_mu(self, value):
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def write_offset_dacs_mu(self, value: int32):
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"""Program the OFS0 and OFS1 offset DAC registers.
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Writes to the offset DACs take effect immediately without requiring
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@ -230,7 +244,7 @@ class AD53xx:
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self.bus.write((AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_OFS1 | value) << 8)
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@kernel
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def write_gain_mu(self, channel, gain=0xffff):
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def write_gain_mu(self, channel: int32, gain: int32 = 0xffff):
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"""Program the gain register for a DAC channel.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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@ -242,7 +256,7 @@ class AD53xx:
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ad53xx_cmd_write_ch(channel, gain, AD53XX_CMD_GAIN) << 8)
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@kernel
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def write_offset_mu(self, channel, offset=0x8000):
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def write_offset_mu(self, channel: int32, offset: int32 = 0x8000):
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"""Program the offset register for a DAC channel.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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@ -254,7 +268,7 @@ class AD53xx:
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ad53xx_cmd_write_ch(channel, offset, AD53XX_CMD_OFFSET) << 8)
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@kernel
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def write_offset(self, channel, voltage):
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def write_offset(self, channel: int32, voltage: float):
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"""Program the DAC offset voltage for a channel.
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An offset of +V can be used to trim out a DAC offset error of -V.
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@ -267,7 +281,7 @@ class AD53xx:
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self.vref))
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@kernel
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def write_dac_mu(self, channel, value):
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def write_dac_mu(self, channel: int32, value: int32):
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"""Program the DAC input register for a channel.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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@ -277,7 +291,7 @@ class AD53xx:
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ad53xx_cmd_write_ch(channel, value, AD53XX_CMD_DATA) << 8)
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@kernel
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def write_dac(self, channel, voltage):
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def write_dac(self, channel: int32, voltage: float):
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"""Program the DAC output voltage for a channel.
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The DAC output is not updated until LDAC is pulsed (see :meth load:).
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@ -299,11 +313,11 @@ class AD53xx:
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This method advances the timeline by two RTIO clock periods.
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"""
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self.ldac.off()
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delay_mu(2*self.bus.ref_period_mu) # t13 = 10ns ldac pulse width low
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delay_mu(int64(2)*self.bus.ref_period_mu) # t13 = 10ns ldac pulse width low
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self.ldac.on()
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@kernel
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def set_dac_mu(self, values, channels=list(range(40))):
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def set_dac_mu(self, values: list[int32], channels: list[int32] = list(range(40))):
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"""Program multiple DAC channels and pulse LDAC to update the DAC
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outputs.
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@ -322,17 +336,19 @@ class AD53xx:
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t0 = now_mu()
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# t10: max busy period after writing to DAC registers
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t_10 = self.core.seconds_to_mu(1500*ns)
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t_10 = self.core.seconds_to_mu(1500.*ns)
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# NAC3TODO len(values) https://git.m-labs.hk/M-Labs/nac3/issues/103
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len_values = 4
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# compensate all delays that will be applied
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delay_mu(-t_10-len(values)*self.bus.xfer_duration_mu)
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for i in range(len(values)):
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delay_mu(-t_10-int64(len_values)*self.bus.xfer_duration_mu)
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for i in range(len_values):
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self.write_dac_mu(channels[i], values[i])
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delay_mu(t_10)
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self.load()
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at_mu(t0)
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@kernel
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def set_dac(self, voltages, channels=list(range(40))):
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def set_dac(self, voltages: list[float], channels: list[int32] = list(range(40))):
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"""Program multiple DAC channels and pulse LDAC to update the DAC
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outputs.
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@ -351,8 +367,8 @@ class AD53xx:
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self.set_dac_mu(values, channels)
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@kernel
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def calibrate(self, channel, vzs, vfs):
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""" Two-point calibration of a DAC channel.
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def calibrate(self, channel: int32, vzs: float, vfs: float):
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"""Two-point calibration of a DAC channel.
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Programs the offset and gain register to trim out DAC errors. Does not
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take effect until LDAC is pulsed (see :meth load:).
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@ -371,15 +387,15 @@ class AD53xx:
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gain_err = voltage_to_mu(vfs, self.offset_dacs, self.vref) - (
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offset_err + 0xffff)
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assert offset_err <= 0
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assert gain_err >= 0
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# NAC3TODO assert offset_err <= 0
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# NAC3TODO assert gain_err >= 0
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self.core.break_realtime()
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self.write_offset_mu(channel, 0x8000-offset_err)
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self.write_gain_mu(channel, 0xffff-gain_err)
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@portable
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def voltage_to_mu(self, voltage):
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def voltage_to_mu(self, voltage: float) -> int32:
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"""Returns the 16-bit DAC register value required to produce a given
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output voltage, assuming offset and gain errors have been trimmed out.
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@ -4,19 +4,23 @@ Output event replacement is not supported and issuing commands at the same
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time is an error.
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"""
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from artiq.language.core import kernel
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from artiq.coredevice import spi2 as spi
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from numpy import int32
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from artiq.language.core import nac3, kernel
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from artiq.coredevice.spi2 import *
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from artiq.coredevice.ad53xx import SPI_AD53XX_CONFIG, AD53xx
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_SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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_SPI_SR_CONFIG = (0*SPI_OFFLINE | 1*SPI_END |
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0*SPI_INPUT | 0*SPI_CS_POLARITY |
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0*SPI_CLK_POLARITY | 0*SPI_CLK_PHASE |
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0*SPI_LSB_FIRST | 0*SPI_HALF_DUPLEX)
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_SPI_CS_DAC = 1
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_SPI_CS_SR = 2
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@nac3
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class Zotino(AD53xx):
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""" Zotino 32-channel, 16-bit 1MSPS DAC.
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@ -42,8 +46,8 @@ class Zotino(AD53xx):
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div_read=div_read, core=core)
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@kernel
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def set_leds(self, leds):
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""" Sets the states of the 8 user LEDs.
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def set_leds(self, leds: int32):
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"""Sets the states of the 8 user LEDs.
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:param leds: 8-bit word with LED state
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"""
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