mirror of https://github.com/m-labs/artiq.git
dma: set conversion granularity using bus width
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@ -3,6 +3,7 @@ from migen.genlib.record import Record, layout_len
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from artiq.gateware.rtio import dma
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from artiq.gateware.rtio.cri import commands as cri_commands
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from artiq.coredevice.comm_analyzer import MessageType, ExceptionType
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@ -42,20 +43,6 @@ assert layout_len(exception_layout) == message_len
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assert layout_len(stopped_layout) == message_len
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def convert_signal(signal):
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assert len(signal) % 8 == 0
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nbytes = len(signal)//8
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assert nbytes % 4 == 0
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nwords = nbytes//4
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signal_words = []
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for i in range(nwords):
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signal_bytes = []
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for j in range(4):
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signal_bytes.append(signal[8*(j+i*4):8*((j+i*4)+1)])
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signal_words.extend(reversed(signal_bytes))
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return Cat(*signal_words)
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class MessageEncoder(Module, AutoCSR):
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def __init__(self, tsc, cri, enable):
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self.source = stream.Endpoint([("data", message_len)])
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@ -150,7 +137,7 @@ class MessageEncoder(Module, AutoCSR):
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class DMAWriter(Module, AutoCSR):
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def __init__(self, membus):
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def __init__(self, membus, cpu_dw):
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aw = len(membus.adr)
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dw = len(membus.dat_w)
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messages_per_dw = dw//message_len
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@ -175,7 +162,7 @@ class DMAWriter(Module, AutoCSR):
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membus.stb.eq(self.sink.stb),
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self.sink.ack.eq(membus.ack),
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membus.we.eq(1),
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membus.dat_w.eq(convert_signal(self.sink.data))
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membus.dat_w.eq(dma.convert_signal(self.sink.data, cpu_dw//8))
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]
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if messages_per_dw > 1:
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for i in range(dw//8):
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@ -207,7 +194,7 @@ class DMAWriter(Module, AutoCSR):
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class Analyzer(Module, AutoCSR):
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def __init__(self, tsc, cri, membus, fifo_depth=128):
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def __init__(self, tsc, cri, membus, fifo_depth=128, cpu_dw=32):
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# shutdown procedure: set enable to 0, wait until busy=0
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self.enable = CSRStorage()
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self.busy = CSRStatus()
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@ -219,7 +206,7 @@ class Analyzer(Module, AutoCSR):
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self.submodules.converter = stream.Converter(
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message_len, len(membus.dat_w), reverse=True,
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report_valid_token_count=True)
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self.submodules.dma = DMAWriter(membus)
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self.submodules.dma = DMAWriter(membus, cpu_dw)
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enable_r = Signal()
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self.sync += [
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@ -11,28 +11,20 @@ def _reverse_bytes(s, g):
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return Cat(reversed(list(s[i*g:(i+1)*g] for i in range(len(s)//g))))
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def reverse_bytes(s):
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n = (len(s) + 7)//8
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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for i in reversed(range(n))])
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def convert_signal(signal):
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def convert_signal(signal, granularity):
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assert len(signal) % 8 == 0
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nbytes = len(signal)//8
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assert nbytes % 4 == 0
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nwords = nbytes//4
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assert nbytes % granularity == 0
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nwords = nbytes//granularity
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signal_words = []
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for i in range(nwords):
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signal_bytes = []
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for j in range(4):
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signal_bytes.append(signal[8*(j+i*4):8*((j+i*4)+1)])
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signal_words.extend(reversed(signal_bytes))
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return Cat(*signal_words)
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signal_words.append(_reverse_bytes(
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signal[i*granularity*8:(i+1)*granularity*8], 8))
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return Cat(signal_words)
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class WishboneReader(Module):
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def __init__(self, bus):
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def __init__(self, bus, cpu_dw):
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self.bus = bus
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aw = len(bus.adr)
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@ -57,18 +49,18 @@ class WishboneReader(Module):
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If(self.source.ack, data_reg_loaded.eq(0)),
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If(bus.ack,
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data_reg_loaded.eq(1),
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self.source.data.eq(convert_signal(bus.dat_r)),
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self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)),
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self.source.eop.eq(self.sink.eop)
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)
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]
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class DMAReader(Module, AutoCSR):
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def __init__(self, membus, enable):
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def __init__(self, membus, enable, cpu_dw):
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aw = len(membus.adr)
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data_alignment = log2_int(len(membus.dat_w)//8)
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self.submodules.wb_reader = WishboneReader(membus)
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self.submodules.wb_reader = WishboneReader(membus, cpu_dw)
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self.source = self.wb_reader.source
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# All numbers in bytes
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@ -344,11 +336,11 @@ class CRIMaster(Module, AutoCSR):
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class DMA(Module):
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def __init__(self, membus):
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def __init__(self, membus, cpu_dw):
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self.enable = CSR()
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flow_enable = Signal()
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self.submodules.dma = DMAReader(membus, flow_enable)
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self.submodules.dma = DMAReader(membus, flow_enable, cpu_dw)
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self.submodules.slicer = RecordSlicer(len(membus.dat_w))
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self.submodules.time_offset = TimeOffset()
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self.submodules.cri_master = CRIMaster()
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