mirror of https://github.com/m-labs/artiq.git
bootloader: add rv32 exception handler
Signed-off-by: occheung <dc@m-labs.hk>
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46102ee737
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@ -17,3 +17,4 @@ byteorder = { version = "1.0", default-features = false }
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crc = { version = "1.7", default-features = false }
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board_misoc = { path = "../libboard_misoc", features = ["uart_console", "smoltcp"] }
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smoltcp = { version = "0.6.0", default-features = false, features = ["ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"] }
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riscv = { version = "0.6.0", features = ["inline-asm"] }
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@ -6,8 +6,9 @@ extern crate byteorder;
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extern crate smoltcp;
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#[macro_use]
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extern crate board_misoc;
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extern crate riscv;
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use core::{ptr, slice};
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use core::{ptr, slice, convert::TryFrom};
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use crc::crc32;
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use byteorder::{ByteOrder, BigEndian};
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use board_misoc::{ident, cache, sdram, config, boot, mem as board_mem};
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@ -16,6 +17,7 @@ use board_misoc::slave_fpga;
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#[cfg(has_ethmac)]
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use board_misoc::{clock, ethmac, net_settings};
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use board_misoc::uart_console::Console;
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use riscv::register::{mcause, mepc};
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fn check_integrity() -> bool {
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extern {
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@ -517,8 +519,10 @@ pub extern fn main() -> i32 {
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}
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#[no_mangle]
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pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
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panic!("exception {} at PC {:#08x}, EA {:#08x}", vect, pc, ea)
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pub extern fn exception(_regs: *const u32) {
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let pc = mepc::read();
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let cause = mcause::read().cause();
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panic!("{:?} at PC {:#08x}", cause, u32::try_from(pc).unwrap())
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}
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#[no_mangle]
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