mirror of https://github.com/m-labs/artiq.git
comm_cpu: select 64b bus if not kasli v1.x
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dd68b4ab82
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@ -104,9 +104,15 @@ class StandaloneBase(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, **kwargs):
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def __init__(self, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
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if hw_rev in ("v1.0", "v1.1"):
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cpu_bus_width = 32
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else:
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cpu_bus_width = 64
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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hw_rev=hw_rev,
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cpu_bus_width=cpu_bus_width,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -255,9 +261,15 @@ class MasterBase(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
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if hw_rev in ("v1.0", "v1.1"):
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cpu_bus_width = 32
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else:
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cpu_bus_width = 64
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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hw_rev=hw_rev,
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cpu_bus_width=cpu_bus_width,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -431,9 +443,15 @@ class SatelliteBase(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
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if hw_rev in ("v1.0", "v1.1"):
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cpu_bus_width = 32
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else:
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cpu_bus_width = 64
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BaseSoC.__init__(self,
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cpu_type="vexriscv",
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hw_rev=hw_rev,
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cpu_bus_width=cpu_bus_width,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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**kwargs)
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@ -132,6 +132,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -209,6 +210,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -342,6 +344,7 @@ class _SatelliteBase(BaseSoC):
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def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -43,6 +43,7 @@ class Master(MiniSoC, AMPSoC):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -57,6 +57,7 @@ class SatelliteBase(MiniSoC):
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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@ -37,6 +37,7 @@ class _SatelliteBase(BaseSoC):
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def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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**kwargs)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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self.rtio_clk_freq = rtio_clk_freq
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