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https://github.com/m-labs/artiq.git
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made kc705/gtx interface more similar to kasli/gtp
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@ -16,7 +16,7 @@ class GTX_20X(Module):
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# * GTX PLL frequency @ 2.5GHz
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# * GTX line rate (TX & RX) @ 2.5Gb/s
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# * GTX TX/RX USRCLK @ 125MHz == coarse RTIO frequency
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def __init__(self, refclk, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq=125e6, tx_mode="single", rx_mode="single"):
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def __init__(self, refclk, pads, sys_clk_freq, rtio_clk_freq=125e6, tx_mode="single", rx_mode="single"):
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assert tx_mode in ["single", "master", "slave"]
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assert rx_mode in ["single", "master", "slave"]
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@ -229,10 +229,10 @@ class GTX_20X(Module):
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p_RXCDR_LOCK_CFG=0b010101,
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# Pads
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i_GTXRXP=rx_pads.p,
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i_GTXRXN=rx_pads.n,
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o_GTXTXP=tx_pads.p,
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o_GTXTXN=tx_pads.n,
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i_GTXRXP=pads.rxp,
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i_GTXRXN=pads.rxn,
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o_GTXTXP=pads.txp,
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o_GTXTXN=pads.txn,
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# Other parameters
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p_PCS_RSVD_ATTR=(
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@ -282,9 +282,8 @@ class GTX_20X(Module):
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class GTX(Module, TransceiverInterface):
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq=125e6, master=0):
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assert len(tx_pads) == len(rx_pads)
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self.nchannels = nchannels = len(tx_pads)
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def __init__(self, clock_pads, pads, sys_clk_freq, rtio_clk_freq=125e6, master=0):
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self.nchannels = nchannels = len(pads)
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self.gtxs = []
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self.rtio_clk_freq = rtio_clk_freq
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@ -307,7 +306,7 @@ class GTX(Module, TransceiverInterface):
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else:
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mode = "master" if i == master else "slave"
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# Note: RX phase alignment is to be done on individual lanes, not multi-lane.
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gtx = GTX_20X(refclk, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq=rtio_clk_freq, tx_mode=mode, rx_mode="single")
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gtx = GTX_20X(refclk, pads[i], sys_clk_freq, rtio_clk_freq=rtio_clk_freq, tx_mode=mode, rx_mode="single")
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# Fan-out (to slave) / Fan-in (from master) of the TXUSRCLK
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if mode == "slave":
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self.comb += gtx.cd_rtio_tx.clk.eq(rtio_tx_clk)
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@ -271,18 +271,14 @@ class _MasterBase(MiniSoC, AMPSoC):
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platform.add_extension(_ams101_dac)
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self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
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tx_pads = [
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platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
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]
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rx_pads = [
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platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
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data_pads = [
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platform.request("sfp"), platform.request("user_sma_mgt")
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]
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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pads=data_pads,
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sys_clk_freq=self.clk_freq)
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self.csr_devices.append("drtio_transceiver")
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@ -405,21 +401,16 @@ class _SatelliteBase(BaseSoC):
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platform.add_extension(_ams101_dac)
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self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
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tx_pads = [
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platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
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]
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rx_pads = [
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platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
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data_pads = [
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platform.request("sfp"), platform.request("user_sma_mgt")
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]
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if sma_as_sat:
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tx_pads = tx_pads[::-1]
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rx_pads = rx_pads[::-1]
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data_pads = data_pads[::-1]
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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pads=data_pads,
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sys_clk_freq=self.clk_freq)
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self.csr_devices.append("drtio_transceiver")
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