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riscv: print mtval on panic

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occheung 2021-10-08 14:41:01 +08:00 committed by Sébastien Bourdeauducq
parent 46326716fd
commit 6d3164a912
4 changed files with 11 additions and 7 deletions
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5
artiq/firmware/bootloader/main.rs
View File

@ -17,7 +17,7 @@ use board_misoc::slave_fpga;
#[cfg(has_ethmac)]
use board_misoc::{clock, ethmac, net_settings};
use board_misoc::uart_console::Console;
use riscv::register::{mcause, mepc};
use riscv::register::{mcause, mepc, mtval};
fn check_integrity() -> bool {
extern {
@ -522,7 +522,8 @@ pub extern fn main() -> i32 {
pub extern fn exception(_regs: *const u32) {
let pc = mepc::read();
let cause = mcause::read().cause();
panic!("{:?} at PC {:#08x}", cause, u32::try_from(pc).unwrap())
let mtval = mtval::read();
panic!("{:?} at PC {:#08x}, trap value {:#08x}", cause, u32::try_from(pc).unwrap(), mtval);
}
#[no_mangle]

3
artiq/firmware/ksupport/lib.rs
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@ -532,7 +532,8 @@ pub unsafe fn main() {
pub extern fn exception(_regs: *const u32) {
let pc = mepc::read();
let cause = mcause::read().cause();
panic!("{:?} at PC {:#08x}", cause, u32::try_from(pc).unwrap())
let mtval = mtval::read();
panic!("{:?} at PC {:#08x}, trap value {:#08x}", cause, u32::try_from(pc).unwrap(), mtval);
}
#[no_mangle]

5
artiq/firmware/runtime/main.rs
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@ -40,7 +40,7 @@ use proto_artiq::{mgmt_proto, moninj_proto, rpc_proto, session_proto, kernel_pro
#[cfg(has_rtio_analyzer)]
use proto_artiq::analyzer_proto;
use riscv::register::{mcause, mepc};
use riscv::register::{mcause, mepc, mtval};
mod rtio_clocking;
mod rtio_mgt;
@ -319,7 +319,8 @@ pub extern fn exception(regs: *const TrapFrame) {
}
hexdump(u32::try_from(pc).unwrap());
panic!("exception {:?} at PC 0x{:x}", e, u32::try_from(pc).unwrap())
let mtval = mtval::read();
panic!("exception {:?} at PC 0x{:x}, trap value 0x{:x}", e, u32::try_from(pc).unwrap(), mtval)
}
}
}

5
artiq/firmware/satman/main.rs
View File

@ -18,7 +18,7 @@ use board_artiq::{spi, drtioaux};
use board_artiq::drtio_routing;
#[cfg(has_hmc830_7043)]
use board_artiq::hmc830_7043;
use riscv::register::{mcause, mepc};
use riscv::register::{mcause, mepc, mtval};
mod repeater;
#[cfg(has_jdcg)]
@ -670,7 +670,8 @@ pub extern fn exception(_regs: *const u32) {
}
hexdump(u32::try_from(pc).unwrap());
panic!("exception {:?} at PC 0x{:x}", cause, u32::try_from(pc).unwrap())
let mtval = mtval::read();
panic!("exception {:?} at PC 0x{:x}, trap value 0x{:x}", cause, u32::try_from(pc).unwrap(), mtval)
}
#[no_mangle]