mirror of https://github.com/m-labs/artiq.git
libboard_misoc: vexriscv integration
Signed-off-by: occheung <dc@m-labs.hk>
This commit is contained in:
parent
2cf144a60c
commit
82b4052cd6
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@ -16,6 +16,8 @@ build_misoc = { path = "../libbuild_misoc" }
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byteorder = { version = "1.0", default-features = false }
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log = { version = "0.4", default-features = false, optional = true }
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smoltcp = { version = "0.6.0", default-features = false, optional = true }
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riscv = { version = "0.6.0", features = ["inline-asm"] }
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vexriscv = { git = "https://github.com/occheung/vexriscv-rust.git", features = ["inline-asm"] }
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[features]
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uart_console = []
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@ -1,5 +1,5 @@
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#![no_std]
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#![feature(asm, try_from)]
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#![feature(llvm_asm)]
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extern crate byteorder;
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#[cfg(feature = "log")]
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@ -11,6 +11,16 @@ extern crate smoltcp;
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#[path = "or1k/mod.rs"]
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mod arch;
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#[cfg(target_arch = "riscv32")]
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#[path = "riscv32imac/mod.rs"]
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mod arch;
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#[cfg(target_arch = "riscv32")]
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extern crate riscv;
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#[cfg(target_arch = "riscv32")]
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extern crate vexriscv;
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pub use arch::*;
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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@ -0,0 +1,48 @@
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use super::{irq, cache};
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pub unsafe fn reset() -> ! {
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irq::set_ie(false);
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llvm_asm!(r#"
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j _reset_handler
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nop
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"# : : : : "volatile");
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loop {}
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}
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pub unsafe fn jump(addr: usize) -> ! {
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irq::set_ie(false);
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cache::flush_cpu_icache();
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llvm_asm!(r#"
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jalr x0, 0($0)
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nop
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"# : : "r"(addr) : : "volatile");
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loop {}
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}
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pub unsafe fn hotswap(firmware: &[u8]) -> ! {
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irq::set_ie(false);
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llvm_asm!(r#"
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# This loop overwrites itself, but it's structured in such a way
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# that before that happens, it loads itself into I$$ fully.
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lui a1, %hi(_reset_handler)
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ori a1, a1, %lo(_reset_handler)
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or a4, a1, zero
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0: bnez a2, 1f
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nop
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jr a4
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nop
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1: lw a3, 0(a0)
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sw a3, 0(a1)
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addi a0, a0, 4
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addi a1, a1, 4
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addi a2, a2, -4
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bnez a2, 0b
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nop
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"#
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:
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: "{a0}"(firmware.as_ptr() as usize),
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"{a2}"(firmware.len())
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:
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: "volatile");
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loop {}
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}
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@ -0,0 +1,35 @@
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#[cfg(has_ddrphy)]
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use core::ptr;
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#[cfg(has_ddrphy)]
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use csr;
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#[cfg(has_ddrphy)]
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use mem;
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pub fn flush_cpu_icache() {
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unsafe {
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llvm_asm!(r#"
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fence.i
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nop
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nop
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nop
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nop
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nop
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"# : : : : "volatile");
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}
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}
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pub fn flush_cpu_dcache() {
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unsafe {
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llvm_asm!(".word(0x500F)" : : : : "volatile");
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}
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}
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#[cfg(has_ddrphy)]
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pub fn flush_l2_cache() {
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unsafe {
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for i in 0..2 * (csr::CONFIG_L2_SIZE as usize) / 4 {
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let addr = mem::MAIN_RAM_BASE + i * 4;
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ptr::read_volatile(addr as *const usize);
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}
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}
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}
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@ -0,0 +1,46 @@
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use core::{convert::TryFrom};
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use riscv::register::mstatus;
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use vexriscv::register::{vmim, vmip};
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#[inline]
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pub fn get_ie() -> bool {
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mstatus::read().mie()
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}
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#[inline]
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pub fn set_ie(ie: bool) {
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unsafe {
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if ie {
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mstatus::set_mie()
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} else {
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mstatus::clear_mie()
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}
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}
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}
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#[inline]
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pub fn get_mask() -> u32 {
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u32::try_from(vmim::read()).unwrap()
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}
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#[inline]
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pub fn set_mask(mask: u32) {
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vmim::write(usize::try_from(mask).unwrap())
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}
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#[inline]
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pub fn pending_mask() -> u32 {
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u32::try_from(vmip::read()).unwrap()
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}
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pub fn enable(irq: u32) {
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set_mask(get_mask() | (1 << irq))
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}
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pub fn disable(irq: u32) {
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set_mask(get_mask() & !(1 << irq))
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}
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pub fn is_pending(irq: u32) -> bool {
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get_mask() & (1 << irq) != 0
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}
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@ -0,0 +1,3 @@
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pub mod irq;
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pub mod cache;
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pub mod boot;
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@ -0,0 +1,177 @@
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# Adapted from riscv-rt project, with the following license:
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#
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# Copyright 2018 RISC-V team
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#
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# Permission to use, copy, modify, and/or distribute this software for any purpose
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# with or without fee is hereby granted, provided that the above copyright notice and
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# this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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# REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
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# FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT,
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# OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA
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# OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
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# ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#if __riscv_xlen == 64
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# define STORE sd
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# define LOAD ld
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# define LOG_REGBYTES 3
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#else
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# define STORE sw
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# define LOAD lw
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# define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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/*
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Entry point of all programs (_reset_handler).
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It initializes DWARF call frame information, the stack pointer, the
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frame pointer (needed for closures to work in start_rust) and the global
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pointer. Then it calls _start_rust.
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*/
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.section .vectors, "ax", @progbits
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.global _reset_handler
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_reset_handler:
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/* Jump to the absolute address defined by the linker script. */
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// for 32bit
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.if __riscv_xlen == 32
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lui ra, %hi(_abs_start)
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jr %lo(_abs_start)(ra)
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.endif
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// for 64bit
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.if __riscv_xlen == 64
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.option push
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.option norelax // to prevent an unsupported R_RISCV_ALIGN relocation from being generated
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1:
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auipc ra, %pcrel_hi(1f)
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ld ra, %pcrel_lo(1b)(ra)
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jr ra
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.align 3
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1:
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.dword _abs_start
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.option pop
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.endif
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_abs_start:
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.cfi_startproc
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.cfi_undefined ra
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csrw mie, 0
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csrw mip, 0
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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// Check hart id
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csrr a2, mhartid
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// Allocate stacks
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la sp, _fstack
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// Set frame pointer
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add s0, sp, zero
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// Set trap vector
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la t0, _start_trap
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csrw mtvec, t0
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// Zero initialize .bss
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la t0, _fbss
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la t1, _ebss
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beq t0, t1, 2f
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1: STORE zero, 0(t0)
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addi t0, t0, REGBYTES
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bne t0, t1, 1b
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2:
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// Enter main firmware
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jal zero, main
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.cfi_endproc
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/*
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Trap entry point (_start_trap)
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Saves caller saved registers ra, t0..6, a0..7, calls exception,
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restores caller saved registers and then returns.
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*/
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.section .trap, "ax"
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.global _start_trap
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/* Make it .weak so PAC/HAL can provide their own if needed. */
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.weak _start_trap
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_start_trap:
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addi sp, sp, -16*REGBYTES
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STORE ra, 0*REGBYTES(sp)
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STORE t0, 1*REGBYTES(sp)
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STORE t1, 2*REGBYTES(sp)
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STORE t2, 3*REGBYTES(sp)
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STORE t3, 4*REGBYTES(sp)
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STORE t4, 5*REGBYTES(sp)
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STORE t5, 6*REGBYTES(sp)
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STORE t6, 7*REGBYTES(sp)
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STORE a0, 8*REGBYTES(sp)
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STORE a1, 9*REGBYTES(sp)
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STORE a2, 10*REGBYTES(sp)
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STORE a3, 11*REGBYTES(sp)
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STORE a4, 12*REGBYTES(sp)
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STORE a5, 13*REGBYTES(sp)
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STORE a6, 14*REGBYTES(sp)
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STORE a7, 15*REGBYTES(sp)
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add a0, sp, zero
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jal ra, exception
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LOAD ra, 0*REGBYTES(sp)
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LOAD t0, 1*REGBYTES(sp)
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LOAD t1, 2*REGBYTES(sp)
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LOAD t2, 3*REGBYTES(sp)
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LOAD t3, 4*REGBYTES(sp)
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LOAD t4, 5*REGBYTES(sp)
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LOAD t5, 6*REGBYTES(sp)
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LOAD t6, 7*REGBYTES(sp)
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LOAD a0, 8*REGBYTES(sp)
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LOAD a1, 9*REGBYTES(sp)
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LOAD a2, 10*REGBYTES(sp)
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LOAD a3, 11*REGBYTES(sp)
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LOAD a4, 12*REGBYTES(sp)
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LOAD a5, 13*REGBYTES(sp)
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LOAD a6, 14*REGBYTES(sp)
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LOAD a7, 15*REGBYTES(sp)
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addi sp, sp, 16*REGBYTES
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mret
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