af28bf3550
simplify dt reset
2022-09-08 08:39:48 +02:00
a91836e5fe
easier fix for dt
2022-09-06 20:26:50 +00:00
27e3c044ed
fix dt computation
2022-09-06 14:32:57 +00:00
3809ac5470
fix type, clean clear
2022-09-02 19:47:06 +00:00
0df2cadcd3
fixes
2022-09-02 15:29:36 +00:00
25c0dc4688
whitespace
2022-09-02 14:54:18 +00:00
cf48232a90
fixes
2022-09-02 14:38:38 +00:00
a20087848d
differentiate phaser modes
2022-09-02 11:03:23 +00:00
31663556b8
phaser: add miqro mode
2022-09-02 09:32:06 +00:00
47f90a58cc
add miqro phy
2022-09-02 09:32:06 +00:00
Mikołaj Sowiński
3c7ab498d1
Added DDS selection for Kasli tester variant
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Signed-off-by: Mikołaj Sowiński <msowinski@technosystem.com.pl>
2022-09-02 17:14:23 +08:00
3535d0f1ae
kasli: relocate the SatelliteBase Error LED code ( #1955 )
2022-08-12 12:41:50 +08:00
cc78078
185c91f522
kasli: add Error LED to MasterBase and SatelliteBase
2022-08-11 15:06:58 +08:00
Alex Wong Tat Hang
a3ae82502c
gtx_7series: fix IBUFGS_GTE2 buffer parameters
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Co-authored-by: topquark12 <aw@m-labs.hk>
2022-08-01 10:21:28 +08:00
8be945d5c7
Urukul monitoring ( #1142 , #1921 )
2022-07-07 10:52:53 +08:00
35f30ddf05
Expose TTLClockGen for Kasli JSONs ( #1886 )
2022-05-06 13:33:42 +08:00
Leon Riesebos
c4292770f8
Kasli JSON description for SPI over DIO cards ( #1800 )
2022-02-26 07:36:00 +08:00
Peter Drmota
4eee49f889
gateware.test.suservo: Fix tests for python >=3.7
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Closes #1748
2022-01-11 17:16:09 +08:00
9eee0e5a7b
gateware/suservo: fix profile no. in test
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Follow-up/Test update for 9d49302
2022-01-11 14:20:47 +08:00
cea0a15e1e
suservo: use default urukul profile
2022-01-10 16:21:39 +08:00
9d493028e5
gateware/suservo: write to profile 7
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Fixes #1817 .
2022-01-07 16:41:19 +08:00
7953f3d705
kc705: add drtio 100mhz clk switch
2021-12-03 17:19:11 +08:00
f281112779
satman: add 100mhz si5324 settings
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siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
eec3ea6589
siphaser: add support for 100mhz rtio
2021-12-03 17:19:11 +08:00
Etienne Wodey
9f830b86c0
kasli: add SED lanes count option to HW description JSON file ( #1745 )
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Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-03 17:05:35 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability ( #1500 )
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* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync
* SUServo: Wrap CPLD and DDS devices in a list
* SUServo: Refactor [nfc]
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
2021-11-15 12:09:16 +08:00
09945ecc4d
gateware: fix drtio/dma tests
2021-11-08 16:59:08 +08:00
cb247f235f
gateware: pass adr_w/data_w to submodules
2021-11-08 16:59:08 +08:00
90f944481c
kernel_cpu: add fpu if not kasli v1.x
2021-11-08 16:59:08 +08:00
d84ad0095b
comm_cpu: select 64b bus if not kasli v1.x
2021-11-08 16:59:08 +08:00
dd68b4ab82
mailbox: parametrize address width
2021-11-08 16:59:08 +08:00
c6e0e26440
drtio: accept 32b/64b bus
2021-11-08 16:59:08 +08:00
8da924ec0f
dma: set conversion granularity using bus width
2021-11-08 16:59:08 +08:00
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
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Fastino cic
2021-10-28 17:44:20 +02:00
0aa8a739aa
sayma_rtm: fix RTM firmware not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
051a14abf2
rtio/dma: fix endianness
2021-09-10 13:25:12 +08:00
a833974b50
analyzer: fix endianness
2021-09-10 13:25:12 +08:00
fc42d053d9
kernel: use vexriscv
2021-09-10 13:25:12 +08:00
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
Mikołaj Sowiński
898122f3e5
Added support for HVAMP_8CH ( #1741 )
2021-08-16 13:39:00 +08:00
7879d3630b
made kc705/gtx interface more similar to kasli/gtp
2021-08-10 18:53:52 +08:00
242dfae38e
kc705: fix DRTIO targets
2021-08-06 15:41:47 +08:00
dc546630e4
kc705: DRTIO variants WIP
2021-08-06 14:41:41 +08:00
fd824f7ad0
ddb_template: print LED channel nos on Kasli v2
2021-08-05 17:29:38 +02:00
ea0c7b6173
Merge remote-tracking branch 'harrydrtio/k7-drtio'
2021-06-15 10:04:45 +08:00
Star Chen
9dee8bb9c9
Kasli: Added front panel user LED ( #1623 ) ( #1694 )
2021-06-07 16:05:50 +08:00
92fd705990
increase memory allocated to comms CPU
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See discussion in #1612 .
2021-02-21 19:06:12 +08:00
d33a206f04
eem: fix Urukul QSPI after 9ef5717de8 (2)
2021-02-12 13:17:48 +08:00
22ce5b0299
eem: fix Urukul QSPI after 9ef5717de8
2021-02-12 10:59:53 +08:00
e54dd08821
metlino,sayma: adapt to new EEM API
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This also enables 4X SERDES TTLs.
2021-02-10 15:32:10 +08:00
547254e89e
eem_7series: pass through kwargs
2021-02-10 15:31:49 +08:00
49299c00a9
eem: enable DCI for LVDS TTL
2021-02-10 15:31:25 +08:00
9ef5717de8
eem: support different I/O standards in EEM slots
2021-02-10 15:31:05 +08:00
461199b903
kasli_generic: warn if min_artiq_version is not met
2021-02-10 15:26:15 +08:00
cf9cf0ab6f
ttl_serdes_7series: add dci (HP bank) support
2021-02-07 22:32:18 +08:00
997a48fb31
ttl_serdes_ultrascale: fix, add dummy dci argument
2021-02-07 22:31:46 +08:00
bbe0c9162a
ttl_serdes_ultrascale: cleanup
2021-02-07 22:00:33 +08:00
3572e2a9c7
ttl_serdes_7series: fix
2021-02-07 21:41:13 +08:00
88c212b84f
ttl_serdes_7series: cleanup
2021-02-07 21:33:21 +08:00
db25f4e8f7
ttl_serdes_7series: use simpler I/O buffers
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In theory equivalent with these parameters.
2021-02-07 20:10:37 +08:00
6bd9691ba8
gateware: remove TTL dead code
2021-02-07 19:58:02 +08:00
bfacd1e5b3
eem: fix Grabber cc_0-2 signal definitions
2021-02-07 18:01:05 +08:00
f7a33a1f99
gateware: make 7-series EEM handling functions shareable
2021-02-07 14:34:26 +08:00
a0fd5261ea
kc705: cleanup
2021-01-22 11:11:13 +08:00
7c4eed7a11
kc705: simplify DRTIO master & satellite
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* KC705 master: user can no longer choose whether or not the SMA acts as the 2nd DRTIO channel; SFP and SMA now act as the 1st and 2nd channel respectively by default.
* KC705 satellite: user should now use `--sma` to enable using the SMA as the satellite channel; SFP acts as the satellite channel by default.
2021-01-22 11:11:13 +08:00
88b14082b6
drtio/transceiver/gtx: delete obsolete modules
2021-01-20 15:05:32 +08:00
9daf77bd58
kc705: add multichannel support on satellite
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* Two DRTIO channels (i.e. satellite and repeater) are enabled by default.
* User can choose either the SFP or SMA as the satellite channel (by passing `--drtio-sat sfp` or --drtio-sat sma` to the argparser), and the unchosen would become the repeater channel.
2021-01-20 15:05:32 +08:00
52afd4ef6b
kc705: add GTX multilane support, add multichannel support on master
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* One DRTIO master channel is enabled by default.
* User can set the SMA as the 2nd master channel (by passing --drtio-sma to the argparser).
* Multi-channel (i.e. with repeaters) on KC705 satellite is supported but has not been implemented yet.
2021-01-20 15:05:32 +08:00
f6d39fd6ba
kc705: revive DRTIO master with updated syntax
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* KC705 master variant now uses Si5324 as synthesiser.
* Multi-channel has not been implemented yet.
2021-01-20 15:05:31 +08:00
f25e86e934
kc705: revive DRTIO satellite with updated syntax, update GTX
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* Multi-channel has not been implemented yet.
2021-01-20 11:25:38 +08:00
c675488a99
reorganize JSON schema files
2021-01-16 10:43:14 +08:00
c6807f4594
kasli_generic: validate description against schema, use defaults from schema
2021-01-16 10:35:23 +08:00
45b5cfce05
gateware: add a kasli_generic.schema.json
2021-01-16 10:35:23 +08:00
cff7bcc122
Merge branch 'master' ( 43be383c86) into k7-drtio
2020-12-31 13:30:46 +08:00
dc7addf394
Revert "drtio: remove KC705/GTX support"
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This reverts commit ebdbaaad32
2020-12-31 13:29:50 +08:00
43ecb3fea6
sayma: add comments about CPLL line rate on KU GTH
2020-12-19 17:05:20 +08:00
8cd794e9f4
jesd204_tools: use new syntax from jesd204b core
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* requires jesd204b changes as in https://github.com/HarryMakes/jesd204b/tree/gth
2020-12-19 17:05:20 +08:00
ccdc741e73
sayma_amc: fix --sfp argument
2020-12-07 18:02:36 +08:00
ea95d91428
wrpll: separate collector reset
2020-11-09 17:57:13 +08:00
a9dd0a268c
Merge pull request #1533 from m-labs/phaser
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Phaser
2020-10-19 09:30:12 +02:00
30d1acee9f
fastlink: fix fastino style link
2020-10-18 20:43:21 +00:00
d98357051c
add ref data
2020-10-18 20:43:21 +00:00
139385a571
fastlink: add fastino test
2020-10-18 17:11:09 +00:00
d185f1ac67
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00
3f076bf79b
wrpll: fix mulshift
2020-10-16 22:05:37 +08:00
hartytp
a058be2ede
wrpll: fix test_helper_collector
2020-10-08 19:43:12 +08:00
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
07d43b6e5f
wrpll: babysit Vivado DSP retiming
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Design now passes timing.
2020-10-08 17:51:27 +08:00
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
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We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
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The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
